1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24 #ifndef _SYS_AUDIOHD_IMPL_H_
  25 #define _SYS_AUDIOHD_IMPL_H_
  26 
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30 
  31 /*
  32  * vendor IDs of PCI audio controllers
  33  */
  34 #define AUDIOHD_VID_ATI         0x1002
  35 #define AUDIOHD_VID_CIRRUS      0x1013
  36 #define AUDIOHD_VID_NVIDIA      0x10de
  37 #define AUDIOHD_VID_REALTEK     0x10ec
  38 #define AUDIOHD_VID_CREATIVE    0x1102
  39 #define AUDIOHD_VID_IDT         0x111d
  40 #define AUDIOHD_VID_ANALOG      0x11d4
  41 #define AUDIOHD_VID_CONEXANT    0x14f1
  42 #define AUDIOHD_VID_SIGMATEL    0x8384
  43 #define AUDIOHD_VID_INTEL       0x8086
  44 
  45 /*
  46  * specific audiohd controller device id
  47  */
  48 #define AUDIOHD_CONTROLLER_MCP51        0x10de026c
  49 
  50 /*
  51  * codec special initial flags
  52  */
  53 #define NO_GPIO         0x00000001
  54 #define NO_MIXER        0x00000002
  55 #define NO_SPDIF        0x00000004
  56 #define EN_PIN_BEEP     0x00000008
  57 
  58 #define AUDIOHD_DEV_CONFIG      "onboard1"
  59 #define AUDIOHD_DEV_VERSION     "a"
  60 
  61 /*
  62  * Only for Intel hardware:
  63  * PCI Express traffic class select register in PCI configure space
  64  */
  65 #define AUDIOHD_INTEL_PCI_TCSEL 0x44
  66 #define AUDIOHD_INTEL_TCS_MASK  0xf8
  67 
  68 /*
  69  * Only for ATI SB450:
  70  * MISC control register 2
  71  */
  72 #define AUDIOHD_ATI_PCI_MISC2   0x42
  73 #define AUDIOHD_ATI_MISC2_MASK  0xf8
  74 #define AUDIOHD_ATI_MISC2_SNOOP 0x02
  75 
  76 /* NVIDIA snoop */
  77 #define AUDIOHD_NVIDIA_SNOOP    0x0f
  78 
  79 #define AUDIOHDC_NID(x)         x
  80 #define AUDIOHDC_NULL_NODE      -1
  81 #define AUDIOHD_NULL_CONN       ((uint_t)(-1))
  82 
  83 #define AUDIOHD_EXT_AMP_MASK    0x00010000
  84 #define AUDIOHD_EXT_AMP_ENABLE  0x02
  85 
  86 /* Power On/Off */
  87 #define AUDIOHD_PW_D0           0
  88 #define AUDIOHD_PW_D2           2
  89 
  90 /* Pin speaker On/Off */
  91 #define AUDIOHD_SP_ON           1
  92 #define AUDIOHD_SP_OFF          0
  93 
  94 #define AUDIOHD_PORT_MAX        15
  95 #define AUDIOHD_CODEC_MAX       16
  96 #define AUDIOHD_MEMIO_LEN       0x4000
  97 
  98 #define AUDIOHD_RETRY_TIMES     60
  99 #define AUDIOHD_TEST_TIMES      500
 100 #define AUDIOHD_OUTSTR_NUM_OFF  12
 101 #define AUDIOHD_INSTR_NUM_OFF   8
 102 
 103 #define AUDIOHD_CORB_SIZE_OFF   0x4e
 104 
 105 #define AUDIOHD_URCAP_MASK      0x80
 106 #define AUDIOHD_DTCCAP_MASK     0x4
 107 #define AUDIOHD_UR_ENABLE_OFF   8
 108 #define AUDIOHD_UR_TAG_MASK     0x3f
 109 
 110 #define AUDIOHD_CIS_MASK        0x40000000
 111 
 112 #define AUDIOHD_RIRB_UR_MASK    0x10
 113 #define AUDIOHD_RIRB_CODEC_MASK 0xf
 114 #define AUDIOHD_RIRB_WID_OFF    27
 115 #define AUDIOHD_RIRB_INTRCNT    0x0
 116 #define AUDIOHD_RIRB_WPMASK     0xff
 117 
 118 #define AUDIOHD_FORM_MASK       0x0080
 119 #define AUDIOHD_LEN_MASK        0x007f
 120 #define AUDIOHD_PIN_CAP_MASK    0x00000010
 121 #define AUDIOHD_PIN_CONF_MASK   0xc0000000
 122 #define AUDIOHD_PIN_CON_MASK    3
 123 #define AUDIOHD_PIN_CON_STEP    30
 124 #define AUDIOHD_PIN_IO_MASK     0X0018
 125 #define AUDIOHD_PIN_SEQ_MASK    0x0000000f
 126 #define AUDIOHD_PIN_ASO_MASK    0x000000f0
 127 #define AUDIOHD_PIN_ASO_OFF     0x4
 128 #define AUDIOHD_PIN_DEV_MASK    0x00f00000
 129 #define AUDIOHD_PIN_DEV_OFF     20
 130 #define AUDIOHD_PIN_NUMS        6
 131 #define AUDIOHD_PIN_NO_CONN     0x40000000
 132 #define AUDIOHD_PIN_IN_ENABLE   0x20
 133 #define AUDIOHD_PIN_OUT_ENABLE  0x40
 134 #define AUDIOHD_PIN_PRES_MASK   0x80000000
 135 #define AUDIOHD_PIN_ELDV_MASK   0x40000000
 136 #define AUDIOHD_PIN_CONTP_OFF   0x1e
 137 #define AUDIOHD_PIN_CON_JACK    0
 138 #define AUDIOHD_PIN_CON_FIXED   0x2
 139 #define AUDIOHD_PIN_CONTP_MASK  0x3
 140 #define AUDIOHD_PIN_VREF_L1     0x20
 141 #define AUDIOHD_PIN_VREF_L2     0x10
 142 #define AUDIOHD_PIN_VREF_L3     0x04
 143 #define AUDIOHD_PIN_VREF_L4     0x02
 144 #define AUDIOHD_PIN_VREF_OFF    8
 145 #define AUDIOHD_PIN_VREF_MASK   0xff
 146 #define AUDIOHD_PIN_CLR_MASK    0xf
 147 #define AUDIOHD_PIN_CLR_OFF     12
 148 
 149 #define AUDIOHD_VERB_ADDR_OFF   28
 150 #define AUDIOHD_VERB_NID_OFF    20
 151 #define AUDIOHD_VERB_CMD_OFF    8
 152 #define AUDIOHD_VERB_CMD16_OFF  16
 153 
 154 #define AUDIOHD_RING_MAX_SIZE   0x00ff
 155 #define AUDIOHD_REC_TAG_OFF     4
 156 #define AUDIOHD_PLAY_TAG_OFF    4
 157 #define AUDIOHD_PLAY_CTL_OFF    2
 158 #define AUDIOHD_REC_CTL_OFF     2
 159 
 160 #define AUDIOHD_SPDIF_ON        1
 161 #define AUDIOHD_SPDIF_MASK      0x00ff
 162 
 163 #define AUDIOHD_GAIN_OFF        8
 164 
 165 #define AUDIOHD_CODEC_STR_OFF   16
 166 #define AUDIOHD_CODEC_STR_MASK  0x000000ff
 167 #define AUDIOHD_CODEC_NUM_MASK  0x000000ff
 168 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff
 169 
 170 #define AUDIOHD_ROUNDUP(x, algn)        (((x) + ((algn) - 1)) & ~((algn) - 1))
 171 #define AUDIOHD_BDLE_BUF_ALIGN  128
 172 #define AUDIOHD_CMDIO_ENT_MASK  0x00ff  /* 256 entries for CORB/RIRB */
 173 #define AUDIOHD_CDBIO_CORB_LEN  1024    /* 256 entries for CORB, 1024B */
 174 #define AUDIOHD_CDBIO_RIRB_LEN  2048    /* 256 entries for RIRB, 2048B */
 175 #define AUDIOHD_BDLE_NUMS       4       /* 4 entires for record/play BD list */
 176 
 177 #define AUDIOHD_PORT_UNMUTE     (0xffffffff)
 178 
 179 /*
 180  * Audio registers of high definition
 181  */
 182 #define AUDIOHD_REG_GCAP                0x00
 183 #define AUDIOHDR_GCAP_OUTSTREAMS        0xf000
 184 #define AUDIOHDR_GCAP_INSTREAMS         0x0f00
 185 #define AUDIOHDR_GCAP_BSTREAMS          0x00f8
 186 #define AUDIOHDR_GCAP_NSDO              0x0006
 187 #define AUDIOHDR_GCAP_64OK              0x0001
 188 
 189 #define AUDIOHD_REG_VMIN                0x02
 190 #define AUDIOHD_REG_VMAJ                0x03
 191 #define AUDIOHD_REG_OUTPAY              0x04
 192 #define AUDIOHD_REG_INPAY               0x06
 193 #define AUDIOHD_REG_GCTL                0x08
 194 #define AUDIOHD_REG_WAKEEN              0x0C
 195 #define AUDIOHD_REG_STATESTS            0x0E
 196 #define AUDIOHD_STATESTS_BIT_SDINS      0x7F
 197 
 198 #define AUDIOHD_REG_GSTS                0x10
 199 #define AUDIOHD_REG_INTCTL              0x20
 200 #define AUDIOHD_INTCTL_BIT_GIE          0x80000000
 201 #define AUDIOHD_INTCTL_BIT_CIE          0x40000000
 202 #define AUDIOHD_INTCTL_BIT_SIE          0x3FFFFFFF
 203 
 204 
 205 #define AUDIOHD_REG_INTSTS              0x24
 206 #define AUDIOHD_INTSTS_BIT_GIS          0x80000000
 207 #define AUDIOHD_INTSTS_BIT_CIS          0x40000000
 208 #define AUDIOHD_INTSTS_BIT_SINTS        (0x3fffffff)
 209 
 210 #define AUDIOHD_REG_WALCLK              0x30
 211 #define AUDIOHD_REG_SYNC                0x38
 212 
 213 #define AUDIOHD_REG_CORBLBASE           0x40
 214 #define AUDIOHD_REG_CORBUBASE           0x44
 215 #define AUDIOHD_REG_CORBWP              0x48
 216 #define AUDIOHD_REG_CORBRP              0x4A
 217 #define AUDIOHD_REG_CORBCTL             0x4C
 218 #define AUDIOHD_REG_CORBST              0x4D
 219 #define AUDIOHD_REG_CORBSIZE            0x4E
 220 
 221 #define AUDIOHD_REG_RIRBLBASE           0x50
 222 #define AUDIOHD_REG_RIRBUBASE           0x54
 223 #define AUDIOHD_REG_RIRBWP              0x58
 224 #define AUDIOHD_REG_RINTCNT             0x5A
 225 #define AUDIOHD_REG_RIRBCTL             0x5C
 226 #define AUDIOHD_REG_RIRBSTS             0x5D
 227 #define AUDIOHD_REG_RIRBSIZE            0x5E
 228 
 229 #define AUDIOHD_REG_IC                  0x60
 230 #define AUDIOHD_REG_IR                  0x64
 231 #define AUDIOHD_REG_IRS                 0x68
 232 #define AUDIOHD_REG_DPLBASE             0x70
 233 #define AUDIOHD_REG_DPUBASE             0x74
 234 
 235 #define AUDIOHD_REG_SD_BASE             0x80
 236 #define AUDIOHD_REG_SD_LEN              0x20
 237 
 238 /*
 239  * Offset of Stream Descriptor Registers
 240  */
 241 #define AUDIOHD_SDREG_OFFSET_CTL                0x00
 242 #define AUDIOHD_SDREG_OFFSET_STS                0x03
 243 #define AUDIOHD_SDREG_OFFSET_LPIB               0x04
 244 #define AUDIOHD_SDREG_OFFSET_CBL                0x08
 245 #define AUDIOHD_SDREG_OFFSET_LVI                0x0c
 246 #define AUDIOHD_SDREG_OFFSET_FIFOW              0x0e
 247 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE           0x10
 248 #define AUDIOHD_SDREG_OFFSET_FORMAT             0x12
 249 #define AUDIOHD_SDREG_OFFSET_BDLPL              0x18
 250 #define AUDIOHD_SDREG_OFFSET_BDLPU              0x1c
 251 
 252 /* bits for stream descriptor control reg */
 253 #define AUDIOHDR_SD_CTL_DEIE            0x000010
 254 #define AUDIOHDR_SD_CTL_FEIE            0x000008
 255 #define AUDIOHDR_SD_CTL_IOCE            0x000004
 256 #define AUDIOHDR_SD_CTL_SRUN            0x000002
 257 #define AUDIOHDR_SD_CTL_SRST            0x000001
 258 
 259 /* bits for stream descriptor status register */
 260 #define AUDIOHDR_SD_STS_BCIS            0x0004
 261 #define AUDIOHDR_SD_STS_FIFOE           0x0008
 262 #define AUDIOHDR_SD_STS_DESE            0x0010
 263 #define AUDIOHDR_SD_STS_FIFORY          0x0020
 264 #define AUDIOHDR_SD_STS_INTRS   \
 265         (AUDIOHDR_SD_STS_BCIS | \
 266         AUDIOHDR_SD_STS_FIFOE | \
 267         AUDIOHDR_SD_STS_DESE)
 268 
 269 /* bits for GCTL register */
 270 #define AUDIOHDR_GCTL_CRST              0x00000001
 271 #define AUDIOHDR_GCTL_URESPE            0x00000100
 272 
 273 /* bits for CORBRP register */
 274 #define AUDIOHDR_CORBRP_RESET           0x8000
 275 #define AUDIOHDR_CORBRP_WPTR            0x00ff
 276 
 277 /* bits for CORBCTL register */
 278 #define AUDIOHDR_CORBCTL_CMEIE          0x01
 279 #define AUDIOHDR_CORBCTL_DMARUN         0x02
 280 
 281 /* bits for CORB SIZE register */
 282 #define AUDIOHDR_CORBSZ_8               0
 283 #define AUDIOHDR_CORBSZ_16              1
 284 #define AUDIOHDR_CORBSZ_256             2
 285 
 286 /* bits for RIRBCTL register */
 287 #define AUDIOHDR_RIRBCTL_RINTCTL        0x01
 288 #define AUDIOHDR_RIRBCTL_DMARUN         0x02
 289 #define AUDIOHDR_RIRBCTL_RIRBOIC        0x04
 290 #define AUDIOHDR_RIRBCTL_RSTINT         0xfe
 291 
 292 /* bits for RIRBWP register */
 293 #define AUDIOHDR_RIRBWP_RESET           0x8000
 294 #define AUDIOHDR_RIRBWP_WPTR            0x00ff
 295 
 296 /* bits for RIRB SIZE register */
 297 #define AUDIOHDR_RIRBSZ_8               0
 298 #define AUDIOHDR_RIRBSZ_16              1
 299 #define AUDIOHDR_RIRBSZ_256             2
 300 
 301 #define AUDIOHD_BDLE_RIRB_SDI           0x0000000f
 302 #define AUDIOHD_BDLE_RIRB_UNSOLICIT     0x00000010
 303 
 304 /* HD spec: ID of Root node is 0 */
 305 #define AUDIOHDC_NODE_ROOT              0x00
 306 
 307 /* HD spec: ID of audio function group is "1" */
 308 #define AUDIOHDC_AUDIO_FUNC_GROUP       1
 309 
 310 /*
 311  * HD audio verbs can be either 12-bit or 4-bit in length.
 312  */
 313 #define AUDIOHDC_12BIT_VERB_MASK        0xfffff000
 314 #define AUDIOHDC_4BIT_VERB_MASK         0xfffffff0
 315 
 316 #define AUDIOHDC_SAMPR48000             48000
 317 #define AUDIOHDC_MAX_BEEP_GEN           12000
 318 #define AUDIOHDC_MIX_BEEP_GEN           47
 319 #define AUDIOHDC_MUTE_BEEP_GEN          0x0
 320 
 321 /*
 322  * 12-bit verbs
 323  */
 324 #define AUDIOHDC_VERB_GET_PARAM                 0xf00
 325 
 326 #define AUDIOHDC_VERB_GET_CONN_SEL              0xf01
 327 #define AUDIOHDC_VERB_SET_CONN_SEL              0x701
 328 
 329 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT         0xf02
 330 #define AUDIOHDC_VERB_GET_PROCESS_STATE         0xf03
 331 #define AUDIOHDC_VERB_GET_SDI_SEL               0xf04
 332 
 333 #define AUDIOHDC_VERB_GET_POWER_STATE           0xf05
 334 #define AUDIOHDC_VERB_SET_POWER_STATE           0x705
 335 
 336 #define AUDIOHDC_VERB_GET_STREAM_CHANN          0xf06
 337 #define AUDIOHDC_VERB_SET_STREAM_CHANN          0x706
 338 
 339 #define AUDIOHDC_VERB_GET_PIN_CTRL              0xf07
 340 #define AUDIOHDC_VERB_SET_PIN_CTRL              0x707
 341 
 342 #define AUDIOHDC_VERB_GET_UNS_ENABLE            0xf08
 343 #define AUDIOHDC_VERB_SET_UNS_ENABLE            0x708
 344 
 345 #define AUDIOHDC_VERB_GET_PIN_SENSE             0xf09
 346 #define AUDIOHDC_VERB_EXEC_PIN_SENSE            0x709
 347 
 348 #define AUDIOHDC_VERB_GET_BEEP_GEN              0xf0a
 349 #define AUDIOHDC_VERB_SET_BEEP_GEN              0x70a
 350 
 351 #define AUDIOHDC_VERB_GET_EAPD                  0xf0c
 352 #define AUDIOHDC_VERB_SET_EAPD                  0x70c
 353 
 354 #define AUDIOHDC_VERB_GET_DEFAULT_CONF          0xf1c
 355 #define AUDIOHDC_VERB_GET_SPDIF_CTL             0xf0d
 356 #define AUDIOHDC_VERB_SET_SPDIF_LCL             0x70d
 357 
 358 #define AUDIOHDC_VERB_GET_GPIO_MASK             0xf16
 359 #define AUDIOHDC_VERB_SET_GPIO_MASK             0x716
 360 
 361 #define AUDIOHDC_VERB_GET_UNSOL_ENABLE_MASK     0xf19
 362 #define AUDIOHDC_VERB_SET_UNSOL_ENABLE_MASK     0x719
 363 
 364 #define AUDIOHDC_VERB_GET_GPIO_DIREC            0xf17
 365 #define AUDIOHDC_VERB_SET_GPIO_DIREC            0x717
 366 
 367 #define AUDIOHDC_VERB_GET_GPIO_DATA             0xf15
 368 #define AUDIOHDC_VERB_SET_GPIO_DATA             0x715
 369 
 370 #define AUDIOHDC_VERB_GET_GPIO_STCK             0xf1a
 371 #define AUDIOHDC_VERB_SET_GPIO_STCK             0x71a
 372 
 373 #define AUDIOHDC_VERB_GET_DIP_SIZE              0xf2e
 374 #define AUDIOHDC_VERB_GET_ELD                   0xf2f
 375 
 376 #define AUDIOHDC_VERB_SET_DIP_INDEX             0x730
 377 #define AUDIOHDC_VERB_SET_DIP_DATA              0x731
 378 #define AUDIOHDC_VERB_SET_DIP_XMIT              0x732
 379 
 380 #define AUDIOHDC_VERB_SET_ASP_CHMAP             0x734
 381 
 382 #define AUDIOHDC_GPIO_ENABLE                    0xff
 383 #define AUDIOHDC_GPIO_DIRECT                    0xf1
 384 
 385 #define AUDIOHDC_GPIO_DATA_CTRL                 0xff
 386 #define AUDIOHDC_GPIO_STCK_CTRL                 0xff
 387 /*
 388  * 4-bit verbs
 389  */
 390 #define AUDIOHDC_VERB_GET_CONV_FMT              0xa
 391 #define AUDIOHDC_VERB_SET_CONV_FMT              0x2
 392 
 393 #define AUDIOHDC_VERB_GET_AMP_MUTE              0xb
 394 #define AUDIOHDC_VERB_SET_AMP_MUTE              0x3
 395 #define AUDIOHDC_VERB_SET_BEEP_VOL              0x3A0
 396 
 397 /*
 398  * parameters of nodes
 399  */
 400 #define AUDIOHDC_PAR_VENDOR_ID                  0x00
 401 #define AUDIOHDC_PAR_SUBSYS_ID                  0x01
 402 #define AUDIOHDC_PAR_REV_ID                     0x02
 403 #define AUDIOHDC_PAR_NODE_COUNT                 0x04
 404 #define AUDIOHDC_PAR_FUNCTION_TYPE              0x05
 405 #define AUDIOHDC_PAR_AUDIO_FG_CAP               0x08
 406 #define AUDIOHDC_PAR_AUDIO_WID_CAP              0x09
 407 #define AUDIOHDC_PAR_PCM                        0x0a
 408 #define AUDIOHDC_PAR_STREAM                     0x0b
 409 #define AUDIOHDC_PAR_PIN_CAP                    0x0c
 410 #define AUDIOHDC_PAR_INAMP_CAP                  0x0d
 411 #define AUDIOHDC_PAR_CONNLIST_LEN               0x0e
 412 #define AUDIOHDC_PAR_POWER_STATE                0x0f
 413 #define AUDIOHDC_PAR_PROC_CAP                   0x10
 414 #define AUDIOHDC_PAR_GPIO_CAP                   0x11
 415 #define AUDIOHDC_PAR_OUTAMP_CAP                 0x12
 416 
 417 /*
 418  * bits for get/set amplifier gain/mute
 419  */
 420 #define AUDIOHDC_AMP_SET_OUTPUT                 0x8000
 421 #define AUDIOHDC_AMP_SET_INPUT                  0x4000
 422 #define AUDIOHDC_AMP_SET_LEFT                   0x2000
 423 #define AUDIOHDC_AMP_SET_RIGHT                  0x1000
 424 #define AUDIOHDC_AMP_SET_MUTE                   0x0080
 425 #define AUDIOHDC_AMP_SET_LNR                    0x3000
 426 #define AUDIOHDC_AMP_SET_LR_INPUT               0x7000
 427 #define AUDIOHDC_AMP_SET_LR_OUTPUT              0xb000
 428 #define AUDIOHDC_AMP_SET_INDEX_OFFSET           8
 429 #define AUDIOHDC_AMP_SET_GAIN_MASK              0x007f
 430 #define AUDIOHDC_GAIN_MAX                       0x7f
 431 #define AUDIOHDC_GAIN_BITS                      7
 432 #define AUDIOHDC_GAIN_DEFAULT                   0x0f
 433 
 434 #define AUDIOHDC_AMP_GET_OUTPUT                 0x8000
 435 #define AUDIOHDC_AMP_GET_INPUT                  0x0000
 436 
 437 /* value used to set max volume for left output */
 438 #define AUDIOHDC_AMP_LOUT_MAX   \
 439         (AUDIOHDC_AMP_SET_OUTPUT | \
 440         AUDIOHDC_AMP_SET_LEFT | \
 441         AUDIOHDC_GAIN_MAX)
 442 
 443 /* value used to set max volume for right output */
 444 #define AUDIOHDC_AMP_ROUT_MAX   \
 445         (AUDIOHDC_AMP_SET_OUTPUT | \
 446         AUDIOHDC_AMP_SET_RIGHT | \
 447         AUDIOHDC_GAIN_MAX)
 448 
 449 
 450 /*
 451  * Bits for pin widget control verb
 452  */
 453 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE          0x80
 454 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE         0x40
 455 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE          0x20
 456 
 457 /*
 458  * Bits for Amplifier capabilities
 459  */
 460 #define AUDIOHDC_AMP_CAP_MUTE_CAP               0x80000000
 461 #define AUDIOHDC_AMP_CAP_STEP_SIZE              0x007f0000
 462 #define AUDIOHDC_AMP_CAP_STEP_NUMS              0x00007f00
 463 #define AUDIOHDC_AMP_CAP_0DB_OFFSET             0x0000007f
 464 
 465 
 466 /*
 467  * Bits for Audio Widget Capabilities
 468  */
 469 #define AUDIOHD_WIDCAP_STEREO           0x00000001
 470 #define AUDIOHD_WIDCAP_INAMP            0x00000002
 471 #define AUDIOHD_WIDCAP_OUTAMP           0x00000004
 472 #define AUDIOHD_WIDCAP_AMP_OVRIDE       0x00000008
 473 #define AUDIOHD_WIDCAP_FMT_OVRIDE       0x00000010
 474 #define AUDIOHD_WIDCAP_STRIP            0x00000020
 475 #define AUDIOHD_WIDCAP_PROC_WID         0x00000040
 476 #define AUDIOHD_WIDCAP_UNSOL            0x00000080
 477 #define AUDIOHD_WIDCAP_CONNLIST         0x00000100
 478 #define AUDIOHD_WIDCAP_DIGIT            0x00000200
 479 #define AUDIOHD_WIDCAP_PWRCTRL          0x00000400
 480 #define AUDIOHD_WIDCAP_LRSWAP           0x00000800
 481 #define AUDIOHD_WIDCAP_TYPE             0x00f00000
 482 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap)         \
 483         ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20)
 484 
 485 #define AUDIOHD_CODEC_FAILURE   (uint32_t)(-1)
 486 
 487 /* Higher sample/bits support */
 488 #define AUDIOHD_BIT_DEPTH16     0x00020000
 489 #define AUDIOHD_BIT_DEPTH24     0x00080000
 490 #define AUDIOHD_SAMP_RATE48     0x00000040
 491 #define AUDIOHD_SAMP_RATE96     0x00000100
 492 #define AUDIOHD_SAMP_RATE192    0x00000400
 493 
 494 /*
 495  * Data Island Packet - Size info
 496  */
 497 #define AUDIOHD_DIP_SIZE_AF             0x0
 498 #define AUDIOHD_DIP_SIZE_ELD            0x8
 499 #define AUDIOHD_DIP_SIZE_ELD_MASK       0xff
 500 
 501 /*
 502  * Data Island Packet - Data
 503  */
 504 #define AUDIOHD_DIP_DATA_LEN            32
 505 
 506 /*
 507  * Data Island Packet - Xmit
 508  */
 509 #define AUDIOHD_DIP_XMIT_STOP           0x00
 510 #define AUDIOHD_DIP_XMIT_ONCE           0x80
 511 #define AUDIOHD_DIP_XMIT_BEST_EFFORT    0xc0
 512 
 513 /*
 514  * EDID-like data (ELD)
 515  */
 516 typedef struct {
 517         uint8_t         sad_nchan:3;
 518         uint8_t         sad_format:4;
 519         uint8_t         sad_rsvd:1;
 520         uint8_t         sad_freq;
 521         uint8_t         sad_bitr;
 522 } audiohd_sad_t;
 523 
 524 #define AUDIOHD_SAD_FORMAT_LPCM         1
 525 #define AUDIOHD_SAD_FORMAT_AC3          2
 526 #define AUDIOHD_SAD_FORMAT_MPEG1        3
 527 #define AUDIOHD_SAD_FORMAT_MP3          4
 528 #define AUDIOHD_SAD_FORMAT_MPEG2        5
 529 #define AUDIOHD_SAD_FORMAT_AAC          6
 530 #define AUDIOHD_SAD_FORMAT_DTS          7
 531 #define AUDIOHD_SAD_FORMAT_ATRAC        8
 532 #define AUDIOHD_SAD_FORMAT_SACD         9
 533 #define AUDIOHD_SAD_FORMAT_DDPLUS       10
 534 #define AUDIOHD_SAD_FORMAT_DTSHD        11
 535 #define AUDIOHD_SAD_FORMAT_MLP          12
 536 #define AUDIOHD_SAD_FORMAT_DST          13
 537 #define AUDIOHD_SAD_FORMAT_WMA          14
 538 
 539 #define AUDIOHD_SAD_FREQ_32             0x1
 540 #define AUDIOHD_SAD_FREQ_44             0x2
 541 #define AUDIOHD_SAD_FREQ_48             0x4
 542 #define AUDIOHD_SAD_FREQ_88             0x8
 543 #define AUDIOHD_SAD_FREQ_96             0x10
 544 #define AUDIOHD_SAD_FREQ_176            0x20
 545 #define AUDIOHD_SAD_FREQ_192            0x40
 546 
 547 #define AUDIOHD_SAD_BITRATE_16          0x1
 548 #define AUDIOHD_SAD_BITRATE_20          0x2
 549 #define AUDIOHD_SAD_BITRATE_24          0x4
 550 
 551 typedef struct {
 552         uint8_t         eld_rsvd1:3;
 553         uint8_t         eld_ver:5;
 554         uint8_t         eld_rsvd2;
 555         uint8_t         eld_baseline_size;
 556         uint8_t         eld_rsvd3;
 557         uint8_t         eld_mnl:5;
 558         uint8_t         eld_cea_edid_ver:3;
 559         uint8_t         eld_hdcp:1;
 560         uint8_t         eld_s_ai:1;
 561         uint8_t         eld_conn_type:2;
 562         uint8_t         eld_sad_count:4;
 563         uint8_t         eld_aud_synch_delay;
 564         uint8_t         eld_channels;
 565         uint64_t        eld_port_id;
 566         char            eld_manufacturer_name[2];
 567         char            eld_product_code[2];
 568         char            eld_monitor_name[16];
 569         audiohd_sad_t   eld_cea_sad[15];
 570         size_t          eld_size;
 571 } audiohd_eld_t;
 572 
 573 #define AUDIOHD_ELD_HDR_LEN     4
 574 
 575 #define AUDIOHD_ELD_VER_2       0x02
 576 #define AUDIOHD_ELD_VER_NODRV   0x1f
 577 #define AUDIOHD_ELD_MAX_MNL     16
 578 #define AUDIOHD_ELD_CEA_861     1
 579 #define AUDIOHD_ELD_CEA_861_A   2
 580 #define AUDIOHD_ELD_CEA_861_BCD 3
 581 
 582 #define AUDIOHD_ELD_CONN_HDMI   0
 583 #define AUDIOHD_ELD_CONN_DP     1
 584 
 585 #define AUDIOHD_ELD_CHAN_FLR    0x01    /* front left/right */
 586 #define AUDIOHD_ELD_CHAN_LFE    0x02    /* low frequency effect */
 587 #define AUDIOHD_ELD_CHAN_FC     0x04    /* front center */
 588 #define AUDIOHD_ELD_CHAN_RLR    0x08    /* rear left/right */
 589 #define AUDIOHD_ELD_CHAN_RC     0x10    /* rear center */
 590 #define AUDIOHD_ELD_CHAN_FLRC   0x20    /* front left/right of center */
 591 #define AUDIOHD_ELD_CHAN_RLRC   0x40    /* rear left/right of center */
 592 
 593 
 594 /*
 595  * buffer descriptor list entry of stream descriptor
 596  */
 597 typedef struct {
 598         uint64_t        sbde_addr;
 599         uint32_t        sbde_len;
 600         uint32_t
 601                 sbde_ioc: 1,
 602                 reserved: 31;
 603 }sd_bdle_t;
 604 
 605 
 606 #define AUDIOHD_PLAY_STARTED            0x00000001
 607 #define AUDIOHD_PLAY_EMPTY              0x00000002
 608 #define AUDIOHD_PLAY_PAUSED             0x00000004
 609 #define AUDIOHD_RECORD_STARTED          0x00000008
 610 
 611 enum audiohda_widget_type {
 612         WTYPE_AUDIO_OUT = 0,
 613         WTYPE_AUDIO_IN,
 614         WTYPE_AUDIO_MIX,
 615         WTYPE_AUDIO_SEL,
 616         WTYPE_PIN,
 617         WTYPE_POWER,
 618         WTYPE_VOL_KNOB,
 619         WTYPE_BEEP,
 620         WTYPE_VENDOR = 0xf
 621 };
 622 
 623 enum audiohda_device_type {
 624         DTYPE_LINEOUT = 0,
 625         DTYPE_SPEAKER,
 626         DTYPE_HP_OUT,
 627         DTYPE_CD,
 628         DTYPE_SPDIF_OUT,
 629         DTYPE_DIGIT_OUT,
 630         DTYPE_MODEM_SIDE,
 631         DTYPE_MODEM_HAND_SIDE,
 632         DTYPE_LINE_IN,
 633         DTYPE_AUX,
 634         DTYPE_MIC_IN,
 635         DTYPE_TEL,
 636         DTYPE_SPDIF_IN,
 637         DTYPE_DIGIT_IN,
 638         DTYPE_OTHER = 0x0f,
 639 };
 640 
 641 enum audiohd_pin_color {
 642         AUDIOHD_PIN_UNKNOWN = 0,
 643         AUDIOHD_PIN_BLACK,
 644         AUDIOHD_PIN_GREY,
 645         AUDIOHD_PIN_BLUE,
 646         AUDIOHD_PIN_GREEN,
 647         AUDIOHD_PIN_RED,
 648         AUDIOHD_PIN_ORANGE,
 649         AUDIOHD_PIN_YELLOW,
 650         AUDIOHD_PIN_PURPLE,
 651         AUDIOHD_PIN_PINK,
 652         AUDIOHD_PIN_WHITE = 0xe,
 653         AUDIOHD_PIN_OTHER = 0xf,
 654 };
 655 
 656 /* values for audiohd_widget.path_flags */
 657 #define AUDIOHD_PATH_DAC        (1 << 0)
 658 #define AUDIOHD_PATH_ADC        (1 << 1)
 659 #define AUDIOHD_PATH_MON        (1 << 2)
 660 #define AUDIOHD_PATH_NOMON      (1 << 3)
 661 #define AUDIOHD_PATH_BEEP       (1 << 4)
 662 #define AUDIOHD_PATH_LOOPBACK   (1 << 5)
 663 
 664 typedef struct audiohd_path     audiohd_path_t;
 665 typedef struct audiohd_widget   audiohd_widget_t;
 666 typedef struct audiohd_state    audiohd_state_t;
 667 typedef struct audiohd_codec_info       audiohd_codec_info_t;
 668 typedef struct audiohd_pin      audiohd_pin_t;
 669 typedef struct hda_codec        hda_codec_t;
 670 typedef uint32_t        wid_t;          /* id of widget */
 671 typedef struct audiohd_entry_prop       audiohd_entry_prop_t;
 672 typedef enum audiohda_device_type       audiohda_device_type_t;
 673 typedef enum audiohd_pin_color          audiohd_pin_color_t;
 674 
 675 #define AUDIOHD_MAX_WIDGET              128
 676 #define AUDIOHD_MAX_CONN                16
 677 #define AUDIOHD_MAX_PINS                16
 678 #define AUDIOHD_MAX_DEPTH               8
 679 
 680 struct audiohd_entry_prop {
 681         uint32_t        conn_len;
 682         uint32_t        mask_range;
 683         uint32_t        mask_wid;
 684         wid_t           input_wid;
 685         int             conns_per_entry;
 686         int             bits_per_conn;
 687 };
 688 struct audiohd_widget {
 689         wid_t           wid_wid;
 690         hda_codec_t     *codec;
 691         enum audiohda_widget_type type;
 692 
 693         uint32_t        widget_cap;
 694         uint32_t        pcm_format;
 695         uint32_t        inamp_cap;
 696         uint32_t        outamp_cap;
 697 
 698         uint32_t        path_flags;
 699 
 700         int             out_weight;
 701         int             in_weight;
 702         int             finish;
 703 
 704         /*
 705          * available (input) connections. 0 means this widget
 706          * has fixed connection
 707          */
 708         int             nconns;
 709 
 710         /*
 711          * wid of possible & selected input & output connections
 712          */
 713         wid_t           avail_conn[AUDIOHD_MAX_CONN];
 714         wid_t           output_path_next;       /* output pin -> DAC */
 715         wid_t           input_path_next;        /* ADC -> input pin */
 716         wid_t           monitor_path_next[AUDIOHD_MAX_CONN];
 717                                                 /* output pin -> input pin */
 718         wid_t           beep_path_next;         /* output pin -> beep widget */
 719         wid_t           loopback_path_next;     /* ADC -> output pin */
 720 
 721         uint16_t        used;
 722 
 723         /*
 724          * pointer to struct depending on widget type:
 725          *      1. DAC  audiohd_path_t
 726          *      2. ADC  audiohd_path_t
 727          *      3. PIN  audiohd_pin_t
 728          */
 729         void    *priv;
 730 };
 731 
 732 #define AUDIOHD_FLAG_LINEOUT            (1 << 0)
 733 #define AUDIOHD_FLAG_SPEAKER            (1 << 1)
 734 #define AUDIOHD_FLAG_HP                 (1 << 2)
 735 #define AUDIOHD_FLAG_MONO               (1 << 3)
 736 
 737 #define AUDIOHD_MAX_MIXER               5
 738 #define AUDIOHD_MAX_PIN                 4
 739 
 740 #define PORT_DAC                0
 741 #define PORT_ADC                1
 742 #define PORT_MAX                2
 743 typedef enum {
 744         PLAY = 0,
 745         RECORD = 1,
 746         BEEP = 2,
 747         LOOPBACK = 3,
 748 } path_type_t;
 749 
 750 struct audiohd_path {
 751         wid_t                   adda_wid;
 752         wid_t                   beep_wid;
 753 
 754         wid_t                   pin_wid[AUDIOHD_MAX_PINS];
 755         int                     sum_selconn[AUDIOHD_MAX_PINS];
 756         int                     mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER];
 757         int                     pin_nums;
 758         int                     maxmixer[AUDIOHD_MAX_PINS];
 759 
 760         path_type_t             path_type;
 761 
 762         wid_t                   mute_wid;
 763         int                     mute_dir;
 764         wid_t                   gain_wid;
 765         int                     gain_dir;
 766         uint32_t                gain_bits;
 767 
 768         uint32_t                pin_outputs;
 769         uint8_t                 tag;
 770 
 771         hda_codec_t             *codec;
 772 
 773         wid_t                   sum_wid;
 774 
 775         audiohd_state_t         *statep;
 776 };
 777 
 778 typedef struct audiohd_port
 779 {
 780         uint8_t                 nchan;
 781         int                     index;
 782         uint16_t                regoff;
 783 
 784         unsigned                nframes;
 785         size_t                  bufsize;
 786         size_t                  fragsize;
 787         uint64_t                count;
 788         int                     curpos;
 789 
 790         uint_t                  format;
 791         unsigned                sync_dir;
 792 
 793         ddi_dma_handle_t        samp_dmah;
 794         ddi_acc_handle_t        samp_acch;
 795         caddr_t                 samp_kaddr;
 796         uint64_t                samp_paddr;
 797 
 798         ddi_dma_handle_t        bdl_dmah;
 799         ddi_acc_handle_t        bdl_acch;
 800         size_t                  bdl_size;
 801         caddr_t                 bdl_kaddr;
 802         uint64_t                bdl_paddr;
 803 
 804         audio_engine_t          *engine;
 805         audiohd_state_t         *statep;
 806 }audiohd_port_t;
 807 
 808 enum {
 809         CTL_VOLUME = 0,
 810         CTL_FRONT,
 811         CTL_SPEAKER,
 812         CTL_HEADPHONE,
 813         CTL_REAR,
 814         CTL_CENTER,
 815         CTL_SURROUND,
 816         CTL_LFE,
 817         CTL_IGAIN,
 818         CTL_LINEIN,
 819         CTL_MIC,
 820         CTL_CD,
 821         CTL_MONGAIN,
 822         CTL_MONSRC,
 823         CTL_RECSRC,
 824         CTL_BEEP,
 825         CTL_LOOP,
 826 
 827         /* this one must be last */
 828         CTL_MAX
 829 };
 830 
 831 typedef struct audiohd_ctrl
 832 {
 833         audiohd_state_t         *statep;
 834         audio_ctrl_t            *ctrl;
 835         int                     num;
 836         uint64_t                val;
 837 } audiohd_ctrl_t;
 838 
 839 struct audiohd_pin {
 840         audiohd_pin_t   *next;
 841         wid_t           wid;
 842         wid_t           mute_wid;       /* node used to mute this pin */
 843         int             mute_dir;       /* 1: input, 2: output */
 844         wid_t           gain_wid;       /* node for gain control */
 845         int             gain_dir;       /* _OUTPUT/_INPUT */
 846         uint32_t        gain_bits;
 847 
 848         uint8_t         vrefvalue;      /* value of VRef */
 849 
 850         uint32_t        cap;
 851         uint32_t        config;
 852         uint32_t        ctrl;
 853         uint32_t        assoc;
 854         uint32_t        seq;
 855         wid_t           adc_wid;
 856         wid_t           dac_wid;
 857         wid_t           beep_wid;
 858         int             no_phys_conn;
 859         enum audiohda_device_type       device;
 860 
 861         /*
 862          * mg_dir, mg_gain, mg_wid are used to store the monitor gain control
 863          * widget wid.
 864          */
 865         int             mg_dir[AUDIOHD_MAX_CONN];
 866         int             mg_gain[AUDIOHD_MAX_CONN];
 867         int             mg_wid[AUDIOHD_MAX_CONN];
 868         int             num;
 869         int             finish;
 870 
 871         /* EDID-like data for HDMI/DP */
 872         audiohd_eld_t   *eld;
 873 };
 874 
 875 typedef struct {
 876         ddi_dma_handle_t        ad_dmahdl;
 877         ddi_acc_handle_t        ad_acchdl;
 878         caddr_t                 ad_vaddr;       /* virtual addr */
 879         uint64_t                ad_paddr;       /* physical addr */
 880         size_t                  ad_req_sz;      /* required size of memory */
 881         size_t                  ad_real_sz;     /* real size of memory */
 882 } audiohd_dma_t;
 883 
 884 struct hda_codec {
 885         uint8_t         index;          /* codec address */
 886         uint32_t        vid;            /* vendor id and device id */
 887         uint32_t        revid;          /* revision id */
 888         wid_t           wid_afg;        /* id of AFG */
 889         wid_t           first_wid;      /* wid of 1st subnode of AFG */
 890         wid_t           last_wid;       /* wid of the last subnode of AFG */
 891         int             nnodes;         /* # of subnodes of AFG */
 892         uint8_t         nistream;
 893 
 894         uint32_t        outamp_cap;
 895         uint32_t        inamp_cap;
 896         uint32_t        stream_format;
 897         uint32_t        pcm_format;
 898 
 899         audiohd_state_t         *statep;
 900         audiohd_codec_info_t    *codec_info;
 901 
 902         /* use wid as index to the array of widget pointers */
 903         audiohd_widget_t        *widget[AUDIOHD_MAX_WIDGET];
 904 
 905         audiohd_port_t          *port[AUDIOHD_PORT_MAX];
 906         uint8_t                 portnum;
 907         audiohd_pin_t           *first_pin;
 908 };
 909 
 910 #define AUDIOHD_MAX_ASSOC       15
 911 struct audiohd_state {
 912         dev_info_t      *hda_dip;
 913         kstat_t         *hda_ksp;
 914         kmutex_t        hda_mutex;
 915         uint32_t        hda_flags;
 916 
 917         caddr_t                 hda_reg_base;
 918         ddi_acc_handle_t        hda_pci_handle;
 919         ddi_acc_handle_t        hda_reg_handle;
 920 
 921         audiohd_dma_t   hda_dma_corb;
 922         audiohd_dma_t   hda_dma_rirb;
 923 
 924         uint8_t         hda_rirb_rp;            /* read pointer for rirb */
 925         uint16_t        hda_codec_mask;
 926 
 927         audio_dev_t     *adev;
 928         uint32_t        devid;
 929 
 930         int             hda_input_streams;      /* # of input stream */
 931         int             hda_output_streams;     /* # of output stream */
 932         int             hda_streams_nums;       /* # of stream */
 933 
 934         uint_t          hda_play_regbase;
 935         uint_t          hda_record_regbase;
 936 
 937         uint_t          hda_play_stag;          /* tag of playback stream */
 938         uint_t          hda_record_stag;        /* tag of record stream */
 939         uint_t          hda_play_lgain;         /* left gain for playback */
 940         uint_t          hda_play_rgain;         /* right gain for playback */
 941 
 942         /*
 943          * Now, for the time being, we add some fields
 944          * for parsing codec topology
 945          */
 946         hda_codec_t     *codec[AUDIOHD_CODEC_MAX];
 947 
 948         /*
 949          * Suspend/Resume used fields
 950          */
 951         boolean_t       suspended;
 952 
 953         audiohd_path_t  *path[AUDIOHD_PORT_MAX];
 954         uint8_t         pathnum;
 955         audiohd_port_t  *port[PORT_MAX];
 956         uint8_t         pchan;
 957         uint8_t         rchan;
 958 
 959         uint64_t        inmask;
 960 
 961         uint_t          hda_out_ports;
 962         uint_t          in_port;
 963 
 964         /* Higher sample/rate */
 965         uint32_t        sample_rate;
 966         uint32_t        sample_bit_depth;
 967         uint8_t         sample_packed_bytes;
 968 
 969         /*
 970          * Controls
 971          */
 972         audiohd_ctrl_t  ctrls[CTL_MAX];
 973         boolean_t       monitor_supported;
 974         boolean_t       loopback_supported;
 975 
 976         /* for multichannel */
 977         uint8_t                 chann[AUDIOHD_MAX_ASSOC];
 978         uint8_t                 assoc;
 979 
 980 };
 981 
 982 struct audiohd_codec_info {
 983         uint32_t        devid;
 984         const char      *buf;
 985         uint32_t        flags;
 986 };
 987 
 988 /*
 989  * Operation for high definition audio control system bus
 990  * interface registers
 991  */
 992 #define AUDIOHD_REG_GET8(reg)   \
 993         ddi_get8(statep->hda_reg_handle, \
 994         (void *)((char *)statep->hda_reg_base + (reg)))
 995 
 996 #define AUDIOHD_REG_GET16(reg)  \
 997         ddi_get16(statep->hda_reg_handle, \
 998         (void *)((char *)statep->hda_reg_base + (reg)))
 999 
1000 #define AUDIOHD_REG_GET32(reg)  \
1001         ddi_get32(statep->hda_reg_handle, \
1002         (void *)((char *)statep->hda_reg_base + (reg)))
1003 
1004 #define AUDIOHD_REG_GET64(reg)  \
1005         ddi_get64(statep->hda_reg_handle, \
1006         (void *)((char *)statep->hda_reg_base + (reg)))
1007 
1008 #define AUDIOHD_REG_SET8(reg, val)      \
1009         ddi_put8(statep->hda_reg_handle, \
1010         (void *)((char *)statep->hda_reg_base + (reg)), (val))
1011 
1012 #define AUDIOHD_REG_SET16(reg, val)     \
1013         ddi_put16(statep->hda_reg_handle, \
1014         (void *)((char *)statep->hda_reg_base + (reg)), (val))
1015 
1016 #define AUDIOHD_REG_SET32(reg, val)     \
1017         ddi_put32(statep->hda_reg_handle, \
1018         (void *)((char *)statep->hda_reg_base + (reg)), (val))
1019 
1020 #define AUDIOHD_REG_SET64(reg, val)     \
1021         ddi_put64(statep->hda_reg_handle, \
1022         (void *)((char *)statep->hda_reg_base + (reg)), (val))
1023 
1024 
1025 /*
1026  * enable a pin widget to input
1027  */
1028 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \
1029 { \
1030         (void) audioha_codec_verb_get(statep, caddr, wid, \
1031             AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \
1032 }
1033 
1034 /*
1035  * disable input pin
1036  */
1037 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \
1038 { \
1039         uint32_t        lTmp; \
1040 \
1041         lTmp = audioha_codec_verb_get(statep, caddr, wid, \
1042             AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
1043         if (lTmp == AUDIOHD_CODEC_FAILURE) \
1044                 return (DDI_FAILURE); \
1045         lTmp = audioha_codec_verb_get(statep, caddr, wid, \
1046             AUDIOHDC_VERB_SET_PIN_CTRL, \
1047             (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \
1048         if (lTmp == AUDIOHD_CODEC_FAILURE) \
1049                 return (DDI_FAILURE); \
1050 }
1051 
1052 /*
1053  * unmute an output pin
1054  */
1055 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \
1056 { \
1057         if (audioha_codec_4bit_verb_get(statep, \
1058             caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \
1059             AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \
1060             AUDIOHD_CODEC_FAILURE) \
1061                 return (DDI_FAILURE); \
1062 }
1063 
1064 /*
1065  * check volume adjust value of 2 channels control
1066  */
1067 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \
1068 { \
1069         if ((value) & ~0xffff) \
1070                 return (EINVAL); \
1071         if ((((value) & 0xff00) >> 8) > 100 || \
1072             ((value) & 0xff) > 100) \
1073                 return (EINVAL); \
1074 }
1075 
1076 /*
1077  * check volume adjust value of mono channel control
1078  */
1079 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \
1080 { \
1081         if ((value) & ~0xff) \
1082                 return (EINVAL); \
1083         if (((value) & 0xff) > 100) \
1084                 return (EINVAL); \
1085 }
1086 
1087 #ifdef __cplusplus
1088 }
1089 #endif
1090 
1091 /* Warlock annotation */
1092 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_ctrl::statep))
1093 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::inmask))
1094 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::adev))
1095 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_bit_depth))
1096 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_rate))
1097 _NOTE(READ_ONLY_DATA(audiohd_state::hda_reg_handle))
1098 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::codec))
1099 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::wid_wid))
1100 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::index))
1101 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::statep))
1102 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::vid))
1103 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::nchan))
1104 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::statep))
1105 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::sync_dir))
1106 
1107 #endif  /* _SYS_AUDIOHD_IMPL_H_ */