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10619 audiohd ignores digital output pins such as HDMI/DP
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--- old/usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
+++ new/usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 #ifndef _SYS_AUDIOHD_IMPL_H_
25 25 #define _SYS_AUDIOHD_IMPL_H_
26 26
27 27 #ifdef __cplusplus
28 28 extern "C" {
29 29 #endif
30 30
31 31 /*
32 32 * vendor IDs of PCI audio controllers
33 33 */
34 34 #define AUDIOHD_VID_ATI 0x1002
35 35 #define AUDIOHD_VID_CIRRUS 0x1013
36 36 #define AUDIOHD_VID_NVIDIA 0x10de
37 37 #define AUDIOHD_VID_REALTEK 0x10ec
38 38 #define AUDIOHD_VID_CREATIVE 0x1102
39 39 #define AUDIOHD_VID_IDT 0x111d
40 40 #define AUDIOHD_VID_ANALOG 0x11d4
41 41 #define AUDIOHD_VID_CONEXANT 0x14f1
42 42 #define AUDIOHD_VID_SIGMATEL 0x8384
43 43 #define AUDIOHD_VID_INTEL 0x8086
44 44
45 45 /*
46 46 * specific audiohd controller device id
47 47 */
48 48 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c
49 49
50 50 /*
51 51 * codec special initial flags
52 52 */
53 53 #define NO_GPIO 0x00000001
54 54 #define NO_MIXER 0x00000002
55 55 #define NO_SPDIF 0x00000004
56 56 #define EN_PIN_BEEP 0x00000008
57 57
58 58 #define AUDIOHD_DEV_CONFIG "onboard1"
59 59 #define AUDIOHD_DEV_VERSION "a"
60 60
61 61 /*
62 62 * Only for Intel hardware:
63 63 * PCI Express traffic class select register in PCI configure space
64 64 */
65 65 #define AUDIOHD_INTEL_PCI_TCSEL 0x44
66 66 #define AUDIOHD_INTEL_TCS_MASK 0xf8
67 67
68 68 /*
69 69 * Only for ATI SB450:
70 70 * MISC control register 2
71 71 */
72 72 #define AUDIOHD_ATI_PCI_MISC2 0x42
73 73 #define AUDIOHD_ATI_MISC2_MASK 0xf8
74 74 #define AUDIOHD_ATI_MISC2_SNOOP 0x02
75 75
76 76 /* NVIDIA snoop */
77 77 #define AUDIOHD_NVIDIA_SNOOP 0x0f
78 78
79 79 #define AUDIOHDC_NID(x) x
80 80 #define AUDIOHDC_NULL_NODE -1
81 81 #define AUDIOHD_NULL_CONN ((uint_t)(-1))
82 82
83 83 #define AUDIOHD_EXT_AMP_MASK 0x00010000
84 84 #define AUDIOHD_EXT_AMP_ENABLE 0x02
85 85
86 86 /* Power On/Off */
87 87 #define AUDIOHD_PW_D0 0
88 88 #define AUDIOHD_PW_D2 2
89 89
90 90 /* Pin speaker On/Off */
91 91 #define AUDIOHD_SP_ON 1
92 92 #define AUDIOHD_SP_OFF 0
93 93
94 94 #define AUDIOHD_PORT_MAX 15
95 95 #define AUDIOHD_CODEC_MAX 16
96 96 #define AUDIOHD_MEMIO_LEN 0x4000
97 97
98 98 #define AUDIOHD_RETRY_TIMES 60
99 99 #define AUDIOHD_TEST_TIMES 500
100 100 #define AUDIOHD_OUTSTR_NUM_OFF 12
101 101 #define AUDIOHD_INSTR_NUM_OFF 8
102 102
103 103 #define AUDIOHD_CORB_SIZE_OFF 0x4e
104 104
105 105 #define AUDIOHD_URCAP_MASK 0x80
106 106 #define AUDIOHD_DTCCAP_MASK 0x4
107 107 #define AUDIOHD_UR_ENABLE_OFF 8
108 108 #define AUDIOHD_UR_TAG_MASK 0x3f
109 109
110 110 #define AUDIOHD_CIS_MASK 0x40000000
111 111
112 112 #define AUDIOHD_RIRB_UR_MASK 0x10
113 113 #define AUDIOHD_RIRB_CODEC_MASK 0xf
114 114 #define AUDIOHD_RIRB_WID_OFF 27
115 115 #define AUDIOHD_RIRB_INTRCNT 0x0
116 116 #define AUDIOHD_RIRB_WPMASK 0xff
117 117
118 118 #define AUDIOHD_FORM_MASK 0x0080
119 119 #define AUDIOHD_LEN_MASK 0x007f
120 120 #define AUDIOHD_PIN_CAP_MASK 0x00000010
121 121 #define AUDIOHD_PIN_CONF_MASK 0xc0000000
122 122 #define AUDIOHD_PIN_CON_MASK 3
123 123 #define AUDIOHD_PIN_CON_STEP 30
124 124 #define AUDIOHD_PIN_IO_MASK 0X0018
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125 125 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f
126 126 #define AUDIOHD_PIN_ASO_MASK 0x000000f0
127 127 #define AUDIOHD_PIN_ASO_OFF 0x4
128 128 #define AUDIOHD_PIN_DEV_MASK 0x00f00000
129 129 #define AUDIOHD_PIN_DEV_OFF 20
130 130 #define AUDIOHD_PIN_NUMS 6
131 131 #define AUDIOHD_PIN_NO_CONN 0x40000000
132 132 #define AUDIOHD_PIN_IN_ENABLE 0x20
133 133 #define AUDIOHD_PIN_OUT_ENABLE 0x40
134 134 #define AUDIOHD_PIN_PRES_MASK 0x80000000
135 +#define AUDIOHD_PIN_ELDV_MASK 0x40000000
135 136 #define AUDIOHD_PIN_CONTP_OFF 0x1e
136 137 #define AUDIOHD_PIN_CON_JACK 0
137 138 #define AUDIOHD_PIN_CON_FIXED 0x2
138 139 #define AUDIOHD_PIN_CONTP_MASK 0x3
139 140 #define AUDIOHD_PIN_VREF_L1 0x20
140 141 #define AUDIOHD_PIN_VREF_L2 0x10
141 142 #define AUDIOHD_PIN_VREF_L3 0x04
142 143 #define AUDIOHD_PIN_VREF_L4 0x02
143 144 #define AUDIOHD_PIN_VREF_OFF 8
144 145 #define AUDIOHD_PIN_VREF_MASK 0xff
145 146 #define AUDIOHD_PIN_CLR_MASK 0xf
146 147 #define AUDIOHD_PIN_CLR_OFF 12
147 148
148 149 #define AUDIOHD_VERB_ADDR_OFF 28
149 150 #define AUDIOHD_VERB_NID_OFF 20
150 151 #define AUDIOHD_VERB_CMD_OFF 8
151 152 #define AUDIOHD_VERB_CMD16_OFF 16
152 153
153 154 #define AUDIOHD_RING_MAX_SIZE 0x00ff
154 155 #define AUDIOHD_REC_TAG_OFF 4
155 156 #define AUDIOHD_PLAY_TAG_OFF 4
156 157 #define AUDIOHD_PLAY_CTL_OFF 2
157 158 #define AUDIOHD_REC_CTL_OFF 2
158 159
159 160 #define AUDIOHD_SPDIF_ON 1
160 161 #define AUDIOHD_SPDIF_MASK 0x00ff
161 162
162 163 #define AUDIOHD_GAIN_OFF 8
163 164
164 165 #define AUDIOHD_CODEC_STR_OFF 16
165 166 #define AUDIOHD_CODEC_STR_MASK 0x000000ff
166 167 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff
167 168 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff
168 169
169 170 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1))
170 171 #define AUDIOHD_BDLE_BUF_ALIGN 128
171 172 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */
172 173 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */
173 174 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */
174 175 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */
175 176
176 177 #define AUDIOHD_PORT_UNMUTE (0xffffffff)
177 178
178 179 /*
179 180 * Audio registers of high definition
180 181 */
181 182 #define AUDIOHD_REG_GCAP 0x00
182 183 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000
183 184 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00
184 185 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8
185 186 #define AUDIOHDR_GCAP_NSDO 0x0006
186 187 #define AUDIOHDR_GCAP_64OK 0x0001
187 188
188 189 #define AUDIOHD_REG_VMIN 0x02
189 190 #define AUDIOHD_REG_VMAJ 0x03
190 191 #define AUDIOHD_REG_OUTPAY 0x04
191 192 #define AUDIOHD_REG_INPAY 0x06
192 193 #define AUDIOHD_REG_GCTL 0x08
193 194 #define AUDIOHD_REG_WAKEEN 0x0C
194 195 #define AUDIOHD_REG_STATESTS 0x0E
195 196 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F
196 197
197 198 #define AUDIOHD_REG_GSTS 0x10
198 199 #define AUDIOHD_REG_INTCTL 0x20
199 200 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000
200 201 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000
201 202 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF
202 203
203 204
204 205 #define AUDIOHD_REG_INTSTS 0x24
205 206 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000
206 207 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000
207 208 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff)
208 209
209 210 #define AUDIOHD_REG_WALCLK 0x30
210 211 #define AUDIOHD_REG_SYNC 0x38
211 212
212 213 #define AUDIOHD_REG_CORBLBASE 0x40
213 214 #define AUDIOHD_REG_CORBUBASE 0x44
214 215 #define AUDIOHD_REG_CORBWP 0x48
215 216 #define AUDIOHD_REG_CORBRP 0x4A
216 217 #define AUDIOHD_REG_CORBCTL 0x4C
217 218 #define AUDIOHD_REG_CORBST 0x4D
218 219 #define AUDIOHD_REG_CORBSIZE 0x4E
219 220
220 221 #define AUDIOHD_REG_RIRBLBASE 0x50
221 222 #define AUDIOHD_REG_RIRBUBASE 0x54
222 223 #define AUDIOHD_REG_RIRBWP 0x58
223 224 #define AUDIOHD_REG_RINTCNT 0x5A
224 225 #define AUDIOHD_REG_RIRBCTL 0x5C
225 226 #define AUDIOHD_REG_RIRBSTS 0x5D
226 227 #define AUDIOHD_REG_RIRBSIZE 0x5E
227 228
228 229 #define AUDIOHD_REG_IC 0x60
229 230 #define AUDIOHD_REG_IR 0x64
230 231 #define AUDIOHD_REG_IRS 0x68
231 232 #define AUDIOHD_REG_DPLBASE 0x70
232 233 #define AUDIOHD_REG_DPUBASE 0x74
233 234
234 235 #define AUDIOHD_REG_SD_BASE 0x80
235 236 #define AUDIOHD_REG_SD_LEN 0x20
236 237
237 238 /*
238 239 * Offset of Stream Descriptor Registers
239 240 */
240 241 #define AUDIOHD_SDREG_OFFSET_CTL 0x00
241 242 #define AUDIOHD_SDREG_OFFSET_STS 0x03
242 243 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04
243 244 #define AUDIOHD_SDREG_OFFSET_CBL 0x08
244 245 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c
245 246 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e
246 247 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10
247 248 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12
248 249 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18
249 250 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c
250 251
251 252 /* bits for stream descriptor control reg */
252 253 #define AUDIOHDR_SD_CTL_DEIE 0x000010
253 254 #define AUDIOHDR_SD_CTL_FEIE 0x000008
254 255 #define AUDIOHDR_SD_CTL_IOCE 0x000004
255 256 #define AUDIOHDR_SD_CTL_SRUN 0x000002
256 257 #define AUDIOHDR_SD_CTL_SRST 0x000001
257 258
258 259 /* bits for stream descriptor status register */
259 260 #define AUDIOHDR_SD_STS_BCIS 0x0004
260 261 #define AUDIOHDR_SD_STS_FIFOE 0x0008
261 262 #define AUDIOHDR_SD_STS_DESE 0x0010
262 263 #define AUDIOHDR_SD_STS_FIFORY 0x0020
263 264 #define AUDIOHDR_SD_STS_INTRS \
264 265 (AUDIOHDR_SD_STS_BCIS | \
265 266 AUDIOHDR_SD_STS_FIFOE | \
266 267 AUDIOHDR_SD_STS_DESE)
267 268
268 269 /* bits for GCTL register */
269 270 #define AUDIOHDR_GCTL_CRST 0x00000001
270 271 #define AUDIOHDR_GCTL_URESPE 0x00000100
271 272
272 273 /* bits for CORBRP register */
273 274 #define AUDIOHDR_CORBRP_RESET 0x8000
274 275 #define AUDIOHDR_CORBRP_WPTR 0x00ff
275 276
276 277 /* bits for CORBCTL register */
277 278 #define AUDIOHDR_CORBCTL_CMEIE 0x01
278 279 #define AUDIOHDR_CORBCTL_DMARUN 0x02
279 280
280 281 /* bits for CORB SIZE register */
281 282 #define AUDIOHDR_CORBSZ_8 0
282 283 #define AUDIOHDR_CORBSZ_16 1
283 284 #define AUDIOHDR_CORBSZ_256 2
284 285
285 286 /* bits for RIRBCTL register */
286 287 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01
287 288 #define AUDIOHDR_RIRBCTL_DMARUN 0x02
288 289 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04
289 290 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe
290 291
291 292 /* bits for RIRBWP register */
292 293 #define AUDIOHDR_RIRBWP_RESET 0x8000
293 294 #define AUDIOHDR_RIRBWP_WPTR 0x00ff
294 295
295 296 /* bits for RIRB SIZE register */
296 297 #define AUDIOHDR_RIRBSZ_8 0
297 298 #define AUDIOHDR_RIRBSZ_16 1
298 299 #define AUDIOHDR_RIRBSZ_256 2
299 300
300 301 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f
301 302 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010
302 303
303 304 /* HD spec: ID of Root node is 0 */
304 305 #define AUDIOHDC_NODE_ROOT 0x00
305 306
306 307 /* HD spec: ID of audio function group is "1" */
307 308 #define AUDIOHDC_AUDIO_FUNC_GROUP 1
308 309
309 310 /*
310 311 * HD audio verbs can be either 12-bit or 4-bit in length.
311 312 */
312 313 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000
313 314 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0
314 315
315 316 #define AUDIOHDC_SAMPR48000 48000
316 317 #define AUDIOHDC_MAX_BEEP_GEN 12000
317 318 #define AUDIOHDC_MIX_BEEP_GEN 47
318 319 #define AUDIOHDC_MUTE_BEEP_GEN 0x0
319 320
320 321 /*
321 322 * 12-bit verbs
322 323 */
323 324 #define AUDIOHDC_VERB_GET_PARAM 0xf00
324 325
325 326 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01
326 327 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701
327 328
328 329 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02
329 330 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03
330 331 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04
331 332
332 333 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05
333 334 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705
334 335
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335 336 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06
336 337 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706
337 338
338 339 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07
339 340 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707
340 341
341 342 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08
342 343 #define AUDIOHDC_VERB_SET_UNS_ENABLE 0x708
343 344
344 345 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09
345 -#define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09
346 346 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709
347 347
348 348 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a
349 349 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a
350 350
351 351 #define AUDIOHDC_VERB_GET_EAPD 0xf0c
352 352 #define AUDIOHDC_VERB_SET_EAPD 0x70c
353 353
354 354 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c
355 355 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d
356 356 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d
357 357
358 358 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16
359 359 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716
360 360
361 361 #define AUDIOHDC_VERB_GET_UNSOL_ENABLE_MASK 0xf19
362 362 #define AUDIOHDC_VERB_SET_UNSOL_ENABLE_MASK 0x719
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363 363
364 364 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17
365 365 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717
366 366
367 367 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15
368 368 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715
369 369
370 370 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a
371 371 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a
372 372
373 +#define AUDIOHDC_VERB_GET_DIP_SIZE 0xf2e
374 +#define AUDIOHDC_VERB_GET_ELD 0xf2f
375 +
376 +#define AUDIOHDC_VERB_SET_DIP_INDEX 0x730
377 +#define AUDIOHDC_VERB_SET_DIP_DATA 0x731
378 +#define AUDIOHDC_VERB_SET_DIP_XMIT 0x732
379 +
380 +#define AUDIOHDC_VERB_SET_ASP_CHMAP 0x734
381 +
373 382 #define AUDIOHDC_GPIO_ENABLE 0xff
374 383 #define AUDIOHDC_GPIO_DIRECT 0xf1
375 384
376 385 #define AUDIOHDC_GPIO_DATA_CTRL 0xff
377 386 #define AUDIOHDC_GPIO_STCK_CTRL 0xff
378 387 /*
379 388 * 4-bit verbs
380 389 */
381 390 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa
382 391 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2
383 392
384 393 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb
385 394 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3
386 395 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0
387 396
388 397 /*
389 398 * parameters of nodes
390 399 */
391 400 #define AUDIOHDC_PAR_VENDOR_ID 0x00
392 401 #define AUDIOHDC_PAR_SUBSYS_ID 0x01
393 402 #define AUDIOHDC_PAR_REV_ID 0x02
394 403 #define AUDIOHDC_PAR_NODE_COUNT 0x04
395 404 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05
396 405 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08
397 406 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09
398 407 #define AUDIOHDC_PAR_PCM 0x0a
399 408 #define AUDIOHDC_PAR_STREAM 0x0b
400 409 #define AUDIOHDC_PAR_PIN_CAP 0x0c
401 410 #define AUDIOHDC_PAR_INAMP_CAP 0x0d
402 411 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e
403 412 #define AUDIOHDC_PAR_POWER_STATE 0x0f
404 413 #define AUDIOHDC_PAR_PROC_CAP 0x10
405 414 #define AUDIOHDC_PAR_GPIO_CAP 0x11
406 415 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12
407 416
408 417 /*
409 418 * bits for get/set amplifier gain/mute
410 419 */
411 420 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000
412 421 #define AUDIOHDC_AMP_SET_INPUT 0x4000
413 422 #define AUDIOHDC_AMP_SET_LEFT 0x2000
414 423 #define AUDIOHDC_AMP_SET_RIGHT 0x1000
415 424 #define AUDIOHDC_AMP_SET_MUTE 0x0080
416 425 #define AUDIOHDC_AMP_SET_LNR 0x3000
417 426 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000
418 427 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000
419 428 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8
420 429 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f
421 430 #define AUDIOHDC_GAIN_MAX 0x7f
422 431 #define AUDIOHDC_GAIN_BITS 7
423 432 #define AUDIOHDC_GAIN_DEFAULT 0x0f
424 433
425 434 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000
426 435 #define AUDIOHDC_AMP_GET_INPUT 0x0000
427 436
428 437 /* value used to set max volume for left output */
429 438 #define AUDIOHDC_AMP_LOUT_MAX \
430 439 (AUDIOHDC_AMP_SET_OUTPUT | \
431 440 AUDIOHDC_AMP_SET_LEFT | \
432 441 AUDIOHDC_GAIN_MAX)
433 442
434 443 /* value used to set max volume for right output */
435 444 #define AUDIOHDC_AMP_ROUT_MAX \
436 445 (AUDIOHDC_AMP_SET_OUTPUT | \
437 446 AUDIOHDC_AMP_SET_RIGHT | \
438 447 AUDIOHDC_GAIN_MAX)
439 448
440 449
441 450 /*
442 451 * Bits for pin widget control verb
443 452 */
444 453 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80
445 454 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40
446 455 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20
447 456
448 457 /*
449 458 * Bits for Amplifier capabilities
450 459 */
451 460 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000
452 461 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000
453 462 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00
454 463 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f
455 464
456 465
457 466 /*
458 467 * Bits for Audio Widget Capabilities
459 468 */
460 469 #define AUDIOHD_WIDCAP_STEREO 0x00000001
461 470 #define AUDIOHD_WIDCAP_INAMP 0x00000002
462 471 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004
463 472 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008
464 473 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010
465 474 #define AUDIOHD_WIDCAP_STRIP 0x00000020
466 475 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040
467 476 #define AUDIOHD_WIDCAP_UNSOL 0x00000080
468 477 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100
469 478 #define AUDIOHD_WIDCAP_DIGIT 0x00000200
470 479 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400
471 480 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800
472 481 #define AUDIOHD_WIDCAP_TYPE 0x00f00000
473 482 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \
474 483 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20)
475 484
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476 485 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1)
477 486
478 487 /* Higher sample/bits support */
479 488 #define AUDIOHD_BIT_DEPTH16 0x00020000
480 489 #define AUDIOHD_BIT_DEPTH24 0x00080000
481 490 #define AUDIOHD_SAMP_RATE48 0x00000040
482 491 #define AUDIOHD_SAMP_RATE96 0x00000100
483 492 #define AUDIOHD_SAMP_RATE192 0x00000400
484 493
485 494 /*
495 + * Data Island Packet - Size info
496 + */
497 +#define AUDIOHD_DIP_SIZE_AF 0x0
498 +#define AUDIOHD_DIP_SIZE_ELD 0x8
499 +#define AUDIOHD_DIP_SIZE_ELD_MASK 0xff
500 +
501 +/*
502 + * Data Island Packet - Data
503 + */
504 +#define AUDIOHD_DIP_DATA_LEN 32
505 +
506 +/*
507 + * Data Island Packet - Xmit
508 + */
509 +#define AUDIOHD_DIP_XMIT_STOP 0x00
510 +#define AUDIOHD_DIP_XMIT_ONCE 0x80
511 +#define AUDIOHD_DIP_XMIT_BEST_EFFORT 0xc0
512 +
513 +/*
514 + * EDID-like data (ELD)
515 + */
516 +typedef struct {
517 + uint8_t sad_nchan:3;
518 + uint8_t sad_format:4;
519 + uint8_t sad_rsvd:1;
520 + uint8_t sad_freq;
521 + uint8_t sad_bitr;
522 +} audiohd_sad_t;
523 +
524 +#define AUDIOHD_SAD_FORMAT_LPCM 1
525 +#define AUDIOHD_SAD_FORMAT_AC3 2
526 +#define AUDIOHD_SAD_FORMAT_MPEG1 3
527 +#define AUDIOHD_SAD_FORMAT_MP3 4
528 +#define AUDIOHD_SAD_FORMAT_MPEG2 5
529 +#define AUDIOHD_SAD_FORMAT_AAC 6
530 +#define AUDIOHD_SAD_FORMAT_DTS 7
531 +#define AUDIOHD_SAD_FORMAT_ATRAC 8
532 +#define AUDIOHD_SAD_FORMAT_SACD 9
533 +#define AUDIOHD_SAD_FORMAT_DDPLUS 10
534 +#define AUDIOHD_SAD_FORMAT_DTSHD 11
535 +#define AUDIOHD_SAD_FORMAT_MLP 12
536 +#define AUDIOHD_SAD_FORMAT_DST 13
537 +#define AUDIOHD_SAD_FORMAT_WMA 14
538 +
539 +#define AUDIOHD_SAD_FREQ_32 0x1
540 +#define AUDIOHD_SAD_FREQ_44 0x2
541 +#define AUDIOHD_SAD_FREQ_48 0x4
542 +#define AUDIOHD_SAD_FREQ_88 0x8
543 +#define AUDIOHD_SAD_FREQ_96 0x10
544 +#define AUDIOHD_SAD_FREQ_176 0x20
545 +#define AUDIOHD_SAD_FREQ_192 0x40
546 +
547 +#define AUDIOHD_SAD_BITRATE_16 0x1
548 +#define AUDIOHD_SAD_BITRATE_20 0x2
549 +#define AUDIOHD_SAD_BITRATE_24 0x4
550 +
551 +typedef struct {
552 + uint8_t eld_rsvd1:3;
553 + uint8_t eld_ver:5;
554 + uint8_t eld_rsvd2;
555 + uint8_t eld_baseline_size;
556 + uint8_t eld_rsvd3;
557 + uint8_t eld_mnl:5;
558 + uint8_t eld_cea_edid_ver:3;
559 + uint8_t eld_hdcp:1;
560 + uint8_t eld_s_ai:1;
561 + uint8_t eld_conn_type:2;
562 + uint8_t eld_sad_count:4;
563 + uint8_t eld_aud_synch_delay;
564 + uint8_t eld_channels;
565 + uint64_t eld_port_id;
566 + char eld_manufacturer_name[2];
567 + char eld_product_code[2];
568 + char eld_monitor_name[16];
569 + audiohd_sad_t eld_cea_sad[15];
570 + size_t eld_size;
571 +} audiohd_eld_t;
572 +
573 +#define AUDIOHD_ELD_HDR_LEN 4
574 +
575 +#define AUDIOHD_ELD_VER_2 0x02
576 +#define AUDIOHD_ELD_VER_NODRV 0x1f
577 +#define AUDIOHD_ELD_MAX_MNL 16
578 +#define AUDIOHD_ELD_CEA_861 1
579 +#define AUDIOHD_ELD_CEA_861_A 2
580 +#define AUDIOHD_ELD_CEA_861_BCD 3
581 +
582 +#define AUDIOHD_ELD_CONN_HDMI 0
583 +#define AUDIOHD_ELD_CONN_DP 1
584 +
585 +#define AUDIOHD_ELD_CHAN_FLR 0x01 /* front left/right */
586 +#define AUDIOHD_ELD_CHAN_LFE 0x02 /* low frequency effect */
587 +#define AUDIOHD_ELD_CHAN_FC 0x04 /* front center */
588 +#define AUDIOHD_ELD_CHAN_RLR 0x08 /* rear left/right */
589 +#define AUDIOHD_ELD_CHAN_RC 0x10 /* rear center */
590 +#define AUDIOHD_ELD_CHAN_FLRC 0x20 /* front left/right of center */
591 +#define AUDIOHD_ELD_CHAN_RLRC 0x40 /* rear left/right of center */
592 +
593 +
594 +/*
486 595 * buffer descriptor list entry of stream descriptor
487 596 */
488 597 typedef struct {
489 598 uint64_t sbde_addr;
490 599 uint32_t sbde_len;
491 600 uint32_t
492 601 sbde_ioc: 1,
493 602 reserved: 31;
494 603 }sd_bdle_t;
495 604
496 605
497 606 #define AUDIOHD_PLAY_STARTED 0x00000001
498 607 #define AUDIOHD_PLAY_EMPTY 0x00000002
499 608 #define AUDIOHD_PLAY_PAUSED 0x00000004
500 609 #define AUDIOHD_RECORD_STARTED 0x00000008
501 610
502 611 enum audiohda_widget_type {
503 612 WTYPE_AUDIO_OUT = 0,
504 613 WTYPE_AUDIO_IN,
505 614 WTYPE_AUDIO_MIX,
506 615 WTYPE_AUDIO_SEL,
507 616 WTYPE_PIN,
508 617 WTYPE_POWER,
509 618 WTYPE_VOL_KNOB,
510 619 WTYPE_BEEP,
511 620 WTYPE_VENDOR = 0xf
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512 621 };
513 622
514 623 enum audiohda_device_type {
515 624 DTYPE_LINEOUT = 0,
516 625 DTYPE_SPEAKER,
517 626 DTYPE_HP_OUT,
518 627 DTYPE_CD,
519 628 DTYPE_SPDIF_OUT,
520 629 DTYPE_DIGIT_OUT,
521 630 DTYPE_MODEM_SIDE,
522 - DTYPE_MODEM_HNAD_SIDE,
631 + DTYPE_MODEM_HAND_SIDE,
523 632 DTYPE_LINE_IN,
524 633 DTYPE_AUX,
525 634 DTYPE_MIC_IN,
526 635 DTYPE_TEL,
527 636 DTYPE_SPDIF_IN,
528 637 DTYPE_DIGIT_IN,
529 638 DTYPE_OTHER = 0x0f,
530 639 };
531 640
532 641 enum audiohd_pin_color {
533 642 AUDIOHD_PIN_UNKNOWN = 0,
534 643 AUDIOHD_PIN_BLACK,
535 644 AUDIOHD_PIN_GREY,
536 645 AUDIOHD_PIN_BLUE,
537 646 AUDIOHD_PIN_GREEN,
538 647 AUDIOHD_PIN_RED,
539 648 AUDIOHD_PIN_ORANGE,
540 649 AUDIOHD_PIN_YELLOW,
541 650 AUDIOHD_PIN_PURPLE,
542 651 AUDIOHD_PIN_PINK,
543 652 AUDIOHD_PIN_WHITE = 0xe,
544 653 AUDIOHD_PIN_OTHER = 0xf,
545 654 };
546 655
547 656 /* values for audiohd_widget.path_flags */
548 657 #define AUDIOHD_PATH_DAC (1 << 0)
549 658 #define AUDIOHD_PATH_ADC (1 << 1)
550 659 #define AUDIOHD_PATH_MON (1 << 2)
551 660 #define AUDIOHD_PATH_NOMON (1 << 3)
552 661 #define AUDIOHD_PATH_BEEP (1 << 4)
553 662 #define AUDIOHD_PATH_LOOPBACK (1 << 5)
554 663
555 664 typedef struct audiohd_path audiohd_path_t;
556 665 typedef struct audiohd_widget audiohd_widget_t;
557 666 typedef struct audiohd_state audiohd_state_t;
558 667 typedef struct audiohd_codec_info audiohd_codec_info_t;
559 668 typedef struct audiohd_pin audiohd_pin_t;
560 669 typedef struct hda_codec hda_codec_t;
561 670 typedef uint32_t wid_t; /* id of widget */
562 671 typedef struct audiohd_entry_prop audiohd_entry_prop_t;
563 672 typedef enum audiohda_device_type audiohda_device_type_t;
564 673 typedef enum audiohd_pin_color audiohd_pin_color_t;
565 674
566 675 #define AUDIOHD_MAX_WIDGET 128
567 676 #define AUDIOHD_MAX_CONN 16
568 677 #define AUDIOHD_MAX_PINS 16
569 678 #define AUDIOHD_MAX_DEPTH 8
570 679
571 680 struct audiohd_entry_prop {
572 681 uint32_t conn_len;
573 682 uint32_t mask_range;
574 683 uint32_t mask_wid;
575 684 wid_t input_wid;
576 685 int conns_per_entry;
577 686 int bits_per_conn;
578 687 };
579 688 struct audiohd_widget {
580 689 wid_t wid_wid;
581 690 hda_codec_t *codec;
582 691 enum audiohda_widget_type type;
583 692
584 693 uint32_t widget_cap;
585 694 uint32_t pcm_format;
586 695 uint32_t inamp_cap;
587 696 uint32_t outamp_cap;
588 697
589 698 uint32_t path_flags;
590 699
591 700 int out_weight;
592 701 int in_weight;
593 702 int finish;
594 703
595 704 /*
596 705 * available (input) connections. 0 means this widget
597 706 * has fixed connection
598 707 */
599 708 int nconns;
600 709
601 710 /*
602 711 * wid of possible & selected input & output connections
603 712 */
604 713 wid_t avail_conn[AUDIOHD_MAX_CONN];
605 714 wid_t output_path_next; /* output pin -> DAC */
606 715 wid_t input_path_next; /* ADC -> input pin */
607 716 wid_t monitor_path_next[AUDIOHD_MAX_CONN];
608 717 /* output pin -> input pin */
609 718 wid_t beep_path_next; /* output pin -> beep widget */
610 719 wid_t loopback_path_next; /* ADC -> output pin */
611 720
612 721 uint16_t used;
613 722
614 723 /*
615 724 * pointer to struct depending on widget type:
616 725 * 1. DAC audiohd_path_t
617 726 * 2. ADC audiohd_path_t
618 727 * 3. PIN audiohd_pin_t
619 728 */
620 729 void *priv;
621 730 };
622 731
623 732 #define AUDIOHD_FLAG_LINEOUT (1 << 0)
624 733 #define AUDIOHD_FLAG_SPEAKER (1 << 1)
625 734 #define AUDIOHD_FLAG_HP (1 << 2)
626 735 #define AUDIOHD_FLAG_MONO (1 << 3)
627 736
628 737 #define AUDIOHD_MAX_MIXER 5
629 738 #define AUDIOHD_MAX_PIN 4
630 739
631 740 #define PORT_DAC 0
632 741 #define PORT_ADC 1
633 742 #define PORT_MAX 2
634 743 typedef enum {
635 744 PLAY = 0,
636 745 RECORD = 1,
637 746 BEEP = 2,
638 747 LOOPBACK = 3,
639 748 } path_type_t;
640 749
641 750 struct audiohd_path {
642 751 wid_t adda_wid;
643 752 wid_t beep_wid;
644 753
645 754 wid_t pin_wid[AUDIOHD_MAX_PINS];
646 755 int sum_selconn[AUDIOHD_MAX_PINS];
647 756 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER];
648 757 int pin_nums;
649 758 int maxmixer[AUDIOHD_MAX_PINS];
650 759
651 760 path_type_t path_type;
652 761
653 762 wid_t mute_wid;
654 763 int mute_dir;
655 764 wid_t gain_wid;
656 765 int gain_dir;
657 766 uint32_t gain_bits;
658 767
659 768 uint32_t pin_outputs;
660 769 uint8_t tag;
661 770
662 771 hda_codec_t *codec;
663 772
664 773 wid_t sum_wid;
665 774
666 775 audiohd_state_t *statep;
667 776 };
668 777
669 778 typedef struct audiohd_port
670 779 {
671 780 uint8_t nchan;
672 781 int index;
673 782 uint16_t regoff;
674 783
675 784 unsigned nframes;
676 785 size_t bufsize;
677 786 size_t fragsize;
678 787 uint64_t count;
679 788 int curpos;
680 789
681 790 uint_t format;
682 791 unsigned sync_dir;
683 792
684 793 ddi_dma_handle_t samp_dmah;
685 794 ddi_acc_handle_t samp_acch;
686 795 caddr_t samp_kaddr;
687 796 uint64_t samp_paddr;
688 797
689 798 ddi_dma_handle_t bdl_dmah;
690 799 ddi_acc_handle_t bdl_acch;
691 800 size_t bdl_size;
692 801 caddr_t bdl_kaddr;
693 802 uint64_t bdl_paddr;
694 803
695 804 audio_engine_t *engine;
696 805 audiohd_state_t *statep;
697 806 }audiohd_port_t;
698 807
699 808 enum {
700 809 CTL_VOLUME = 0,
701 810 CTL_FRONT,
702 811 CTL_SPEAKER,
703 812 CTL_HEADPHONE,
704 813 CTL_REAR,
705 814 CTL_CENTER,
706 815 CTL_SURROUND,
707 816 CTL_LFE,
708 817 CTL_IGAIN,
709 818 CTL_LINEIN,
710 819 CTL_MIC,
711 820 CTL_CD,
712 821 CTL_MONGAIN,
713 822 CTL_MONSRC,
714 823 CTL_RECSRC,
715 824 CTL_BEEP,
716 825 CTL_LOOP,
717 826
718 827 /* this one must be last */
719 828 CTL_MAX
720 829 };
721 830
722 831 typedef struct audiohd_ctrl
723 832 {
724 833 audiohd_state_t *statep;
725 834 audio_ctrl_t *ctrl;
726 835 int num;
727 836 uint64_t val;
728 837 } audiohd_ctrl_t;
729 838
730 839 struct audiohd_pin {
731 840 audiohd_pin_t *next;
732 841 wid_t wid;
733 842 wid_t mute_wid; /* node used to mute this pin */
734 843 int mute_dir; /* 1: input, 2: output */
735 844 wid_t gain_wid; /* node for gain control */
736 845 int gain_dir; /* _OUTPUT/_INPUT */
737 846 uint32_t gain_bits;
738 847
739 848 uint8_t vrefvalue; /* value of VRef */
740 849
741 850 uint32_t cap;
742 851 uint32_t config;
743 852 uint32_t ctrl;
744 853 uint32_t assoc;
745 854 uint32_t seq;
746 855 wid_t adc_wid;
747 856 wid_t dac_wid;
748 857 wid_t beep_wid;
749 858 int no_phys_conn;
750 859 enum audiohda_device_type device;
751 860
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752 861 /*
753 862 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control
754 863 * widget wid.
755 864 */
756 865 int mg_dir[AUDIOHD_MAX_CONN];
757 866 int mg_gain[AUDIOHD_MAX_CONN];
758 867 int mg_wid[AUDIOHD_MAX_CONN];
759 868 int num;
760 869 int finish;
761 870
871 + /* EDID-like data for HDMI/DP */
872 + audiohd_eld_t *eld;
762 873 };
763 874
764 875 typedef struct {
765 876 ddi_dma_handle_t ad_dmahdl;
766 877 ddi_acc_handle_t ad_acchdl;
767 878 caddr_t ad_vaddr; /* virtual addr */
768 879 uint64_t ad_paddr; /* physical addr */
769 880 size_t ad_req_sz; /* required size of memory */
770 881 size_t ad_real_sz; /* real size of memory */
771 882 } audiohd_dma_t;
772 883
773 884 struct hda_codec {
774 885 uint8_t index; /* codec address */
775 886 uint32_t vid; /* vendor id and device id */
776 887 uint32_t revid; /* revision id */
777 888 wid_t wid_afg; /* id of AFG */
778 889 wid_t first_wid; /* wid of 1st subnode of AFG */
779 890 wid_t last_wid; /* wid of the last subnode of AFG */
780 891 int nnodes; /* # of subnodes of AFG */
781 892 uint8_t nistream;
782 893
783 894 uint32_t outamp_cap;
784 895 uint32_t inamp_cap;
785 896 uint32_t stream_format;
786 897 uint32_t pcm_format;
787 898
788 899 audiohd_state_t *statep;
789 900 audiohd_codec_info_t *codec_info;
790 901
791 902 /* use wid as index to the array of widget pointers */
792 903 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET];
793 904
794 905 audiohd_port_t *port[AUDIOHD_PORT_MAX];
795 906 uint8_t portnum;
796 907 audiohd_pin_t *first_pin;
797 908 };
798 909
799 910 #define AUDIOHD_MAX_ASSOC 15
800 911 struct audiohd_state {
801 912 dev_info_t *hda_dip;
802 913 kstat_t *hda_ksp;
803 914 kmutex_t hda_mutex;
804 915 uint32_t hda_flags;
805 916
806 917 caddr_t hda_reg_base;
807 918 ddi_acc_handle_t hda_pci_handle;
808 919 ddi_acc_handle_t hda_reg_handle;
809 920
810 921 audiohd_dma_t hda_dma_corb;
811 922 audiohd_dma_t hda_dma_rirb;
812 923
813 924 uint8_t hda_rirb_rp; /* read pointer for rirb */
814 925 uint16_t hda_codec_mask;
815 926
816 927 audio_dev_t *adev;
817 928 uint32_t devid;
818 929
819 930 int hda_input_streams; /* # of input stream */
820 931 int hda_output_streams; /* # of output stream */
821 932 int hda_streams_nums; /* # of stream */
822 933
823 934 uint_t hda_play_regbase;
824 935 uint_t hda_record_regbase;
825 936
826 937 uint_t hda_play_stag; /* tag of playback stream */
827 938 uint_t hda_record_stag; /* tag of record stream */
828 939 uint_t hda_play_lgain; /* left gain for playback */
829 940 uint_t hda_play_rgain; /* right gain for playback */
830 941
831 942 /*
832 943 * Now, for the time being, we add some fields
833 944 * for parsing codec topology
834 945 */
835 946 hda_codec_t *codec[AUDIOHD_CODEC_MAX];
836 947
837 948 /*
838 949 * Suspend/Resume used fields
839 950 */
840 951 boolean_t suspended;
841 952
842 953 audiohd_path_t *path[AUDIOHD_PORT_MAX];
843 954 uint8_t pathnum;
844 955 audiohd_port_t *port[PORT_MAX];
845 956 uint8_t pchan;
846 957 uint8_t rchan;
847 958
848 959 uint64_t inmask;
849 960
850 961 uint_t hda_out_ports;
851 962 uint_t in_port;
852 963
853 964 /* Higher sample/rate */
854 965 uint32_t sample_rate;
855 966 uint32_t sample_bit_depth;
856 967 uint8_t sample_packed_bytes;
857 968
858 969 /*
859 970 * Controls
860 971 */
861 972 audiohd_ctrl_t ctrls[CTL_MAX];
862 973 boolean_t monitor_supported;
863 974 boolean_t loopback_supported;
864 975
865 976 /* for multichannel */
866 977 uint8_t chann[AUDIOHD_MAX_ASSOC];
867 978 uint8_t assoc;
868 979
869 980 };
870 981
871 982 struct audiohd_codec_info {
872 983 uint32_t devid;
873 984 const char *buf;
874 985 uint32_t flags;
875 986 };
876 987
877 988 /*
878 989 * Operation for high definition audio control system bus
879 990 * interface registers
880 991 */
881 992 #define AUDIOHD_REG_GET8(reg) \
882 993 ddi_get8(statep->hda_reg_handle, \
883 994 (void *)((char *)statep->hda_reg_base + (reg)))
884 995
885 996 #define AUDIOHD_REG_GET16(reg) \
886 997 ddi_get16(statep->hda_reg_handle, \
887 998 (void *)((char *)statep->hda_reg_base + (reg)))
888 999
889 1000 #define AUDIOHD_REG_GET32(reg) \
890 1001 ddi_get32(statep->hda_reg_handle, \
891 1002 (void *)((char *)statep->hda_reg_base + (reg)))
892 1003
893 1004 #define AUDIOHD_REG_GET64(reg) \
894 1005 ddi_get64(statep->hda_reg_handle, \
895 1006 (void *)((char *)statep->hda_reg_base + (reg)))
896 1007
897 1008 #define AUDIOHD_REG_SET8(reg, val) \
898 1009 ddi_put8(statep->hda_reg_handle, \
899 1010 (void *)((char *)statep->hda_reg_base + (reg)), (val))
900 1011
901 1012 #define AUDIOHD_REG_SET16(reg, val) \
902 1013 ddi_put16(statep->hda_reg_handle, \
903 1014 (void *)((char *)statep->hda_reg_base + (reg)), (val))
904 1015
905 1016 #define AUDIOHD_REG_SET32(reg, val) \
906 1017 ddi_put32(statep->hda_reg_handle, \
907 1018 (void *)((char *)statep->hda_reg_base + (reg)), (val))
908 1019
909 1020 #define AUDIOHD_REG_SET64(reg, val) \
910 1021 ddi_put64(statep->hda_reg_handle, \
911 1022 (void *)((char *)statep->hda_reg_base + (reg)), (val))
912 1023
913 1024
914 1025 /*
915 1026 * enable a pin widget to input
916 1027 */
917 1028 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \
918 1029 { \
919 1030 (void) audioha_codec_verb_get(statep, caddr, wid, \
920 1031 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \
921 1032 }
922 1033
923 1034 /*
924 1035 * disable input pin
925 1036 */
926 1037 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \
927 1038 { \
928 1039 uint32_t lTmp; \
929 1040 \
930 1041 lTmp = audioha_codec_verb_get(statep, caddr, wid, \
931 1042 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
932 1043 if (lTmp == AUDIOHD_CODEC_FAILURE) \
933 1044 return (DDI_FAILURE); \
934 1045 lTmp = audioha_codec_verb_get(statep, caddr, wid, \
935 1046 AUDIOHDC_VERB_SET_PIN_CTRL, \
936 1047 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \
937 1048 if (lTmp == AUDIOHD_CODEC_FAILURE) \
938 1049 return (DDI_FAILURE); \
939 1050 }
940 1051
941 1052 /*
942 1053 * unmute an output pin
943 1054 */
944 1055 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \
945 1056 { \
946 1057 if (audioha_codec_4bit_verb_get(statep, \
947 1058 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \
948 1059 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \
949 1060 AUDIOHD_CODEC_FAILURE) \
950 1061 return (DDI_FAILURE); \
951 1062 }
952 1063
953 1064 /*
954 1065 * check volume adjust value of 2 channels control
955 1066 */
956 1067 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \
957 1068 { \
958 1069 if ((value) & ~0xffff) \
959 1070 return (EINVAL); \
960 1071 if ((((value) & 0xff00) >> 8) > 100 || \
961 1072 ((value) & 0xff) > 100) \
962 1073 return (EINVAL); \
963 1074 }
964 1075
965 1076 /*
966 1077 * check volume adjust value of mono channel control
967 1078 */
968 1079 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \
969 1080 { \
970 1081 if ((value) & ~0xff) \
971 1082 return (EINVAL); \
972 1083 if (((value) & 0xff) > 100) \
973 1084 return (EINVAL); \
974 1085 }
975 1086
976 1087 #ifdef __cplusplus
977 1088 }
978 1089 #endif
979 1090
980 1091 /* Warlock annotation */
981 1092 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_ctrl::statep))
982 1093 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::inmask))
983 1094 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::adev))
984 1095 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_bit_depth))
985 1096 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_rate))
986 1097 _NOTE(READ_ONLY_DATA(audiohd_state::hda_reg_handle))
987 1098 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::codec))
988 1099 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::wid_wid))
989 1100 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::index))
990 1101 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::statep))
991 1102 _NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::vid))
992 1103 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::nchan))
993 1104 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::statep))
994 1105 _NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::sync_dir))
995 1106
996 1107 #endif /* _SYS_AUDIOHD_IMPL_H_ */
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