143 "asysc",
144 "nx",
145 "sse3",
146 "cx16",
147 "cmp",
148 "tscp",
149 "mwait",
150 "sse4a",
151 "cpuid",
152 "ssse3",
153 "sse4_1",
154 "sse4_2",
155 "1gpg",
156 "clfsh",
157 "64",
158 "aes",
159 "pclmulqdq",
160 "xsave",
161 "avx",
162 "vmx",
163 "svm"
164 };
165
166 boolean_t
167 is_x86_feature(void *featureset, uint_t feature)
168 {
169 ASSERT(feature < NUM_X86_FEATURES);
170 return (BT_TEST((ulong_t *)featureset, feature));
171 }
172
173 void
174 add_x86_feature(void *featureset, uint_t feature)
175 {
176 ASSERT(feature < NUM_X86_FEATURES);
177 BT_SET((ulong_t *)featureset, feature);
178 }
179
180 void
181 remove_x86_feature(void *featureset, uint_t feature)
182 {
183 ASSERT(feature < NUM_X86_FEATURES);
252 * Note: the kernel will use the maximum size required for all hardware
253 * features. It is not optimize for potential memory savings if features at
254 * the end of the save area are not enabled.
255 */
256 struct xsave_info {
257 uint32_t xsav_hw_features_low; /* Supported HW features */
258 uint32_t xsav_hw_features_high; /* Supported HW features */
259 size_t xsav_max_size; /* max size save area for HW features */
260 size_t ymm_size; /* AVX: size of ymm save area */
261 size_t ymm_offset; /* AVX: offset for ymm save area */
262 };
263
264
265 /*
266 * These constants determine how many of the elements of the
267 * cpuid we cache in the cpuid_info data structure; the
268 * remaining elements are accessible via the cpuid instruction.
269 */
270
271 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
272 #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */
273
274 /*
275 * Some terminology needs to be explained:
276 * - Socket: Something that can be plugged into a motherboard.
277 * - Package: Same as socket
278 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
279 * differently: there, chip is the same as processor node (below)
280 * - Processor node: Some AMD processors have more than one
281 * "subprocessor" embedded in a package. These subprocessors (nodes)
282 * are fully-functional processors themselves with cores, caches,
283 * memory controllers, PCI configuration spaces. They are connected
284 * inside the package with Hypertransport links. On single-node
285 * processors, processor node is equivalent to chip/socket/package.
286 */
287
288 struct cpuid_info {
289 uint_t cpi_pass; /* last pass completed */
290 /*
291 * standard function information
292 */
293 uint_t cpi_maxeax; /* fn 0: %eax */
294 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
295 uint_t cpi_vendor; /* enum of cpi_vendorstr */
296
297 uint_t cpi_family; /* fn 1: extended family */
298 uint_t cpi_model; /* fn 1: extended model */
299 uint_t cpi_step; /* fn 1: stepping */
300 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
301 /* AMD: package/socket # */
302 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
303 int cpi_clogid; /* fn 1: %ebx: thread # */
304 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
305 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
326 * supported feature information
327 */
328 uint32_t cpi_support[5];
329 #define STD_EDX_FEATURES 0
330 #define AMD_EDX_FEATURES 1
331 #define TM_EDX_FEATURES 2
332 #define STD_ECX_FEATURES 3
333 #define AMD_ECX_FEATURES 4
334 /*
335 * Synthesized information, where known.
336 */
337 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
338 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
339 uint32_t cpi_socket; /* Chip package/socket type */
340
341 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
342 uint32_t cpi_apicid;
343 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
344 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
345 /* Intel: 1 */
346
347 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
348 };
349
350
351 static struct cpuid_info cpuid_info0;
352
353 /*
354 * These bit fields are defined by the Intel Application Note AP-485
355 * "Intel Processor Identification and the CPUID Instruction"
356 */
357 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
358 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
359 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
360 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
361 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
362 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
363
364 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
365 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
710 * Where the number of bits necessary to
711 * represent MC and HT fields together equals
712 * to the minimum number of bits necessary to
713 * store the value of cpi->cpi_ncpu_per_chip.
714 * Of those bits, the MC part uses the number
715 * of bits necessary to store the value of
716 * cpi->cpi_ncore_per_chip.
717 */
718 for (i = 1; i < ncpu_per_core; i <<= 1)
719 coreid_shift++;
720 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
721 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
722 } else if (is_x86_feature(feature, X86FSET_HTT)) {
723 /*
724 * Single-core multi-threaded processors.
725 */
726 cpi->cpi_coreid = cpi->cpi_chipid;
727 cpi->cpi_pkgcoreid = 0;
728 }
729 cpi->cpi_procnodeid = cpi->cpi_chipid;
730 }
731
732 static void
733 cpuid_amd_getids(cpu_t *cpu)
734 {
735 int i, first_half, coreidsz;
736 uint32_t nb_caps_reg;
737 uint_t node2_1;
738 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
739
740 /*
741 * AMD CMP chips currently have a single thread per core.
742 *
743 * Since no two cpus share a core we must assign a distinct coreid
744 * per cpu, and we do this by using the cpu_id. This scheme does not,
745 * however, guarantee that sibling cores of a chip will have sequential
746 * coreids starting at a multiple of the number of cores per chip -
747 * that is usually the case, but if the ACPI MADT table is presented
748 * in a different order then we need to perform a few more gymnastics
749 * for the pkgcoreid.
750 *
751 * All processors in the system have the same number of enabled
752 * cores. Cores within a processor are always numbered sequentially
753 * from 0 regardless of how many or which are disabled, and there
754 * is no way for operating system to discover the real core id when some
755 * are disabled.
756 */
757
758 cpi->cpi_coreid = cpu->cpu_id;
759
760 if (cpi->cpi_xmaxeax >= 0x80000008) {
761
762 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
763
764 /*
765 * In AMD parlance chip is really a node while Solaris
766 * sees chip as equivalent to socket/package.
767 */
768 cpi->cpi_ncore_per_chip =
769 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
770 if (coreidsz == 0) {
771 /* Use legacy method */
772 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
773 coreidsz++;
774 if (coreidsz == 0)
775 coreidsz = 1;
776 }
777 } else {
778 /* Assume single-core part */
779 cpi->cpi_ncore_per_chip = 1;
780 coreidsz = 1;
781 }
782
783 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
784 cpi->cpi_apicid & ((1<<coreidsz) - 1);
785 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
786
787 /* Get nodeID */
788 if (cpi->cpi_family == 0xf) {
789 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
790 cpi->cpi_chipid = cpi->cpi_procnodeid;
791 } else if (cpi->cpi_family == 0x10) {
792 /*
793 * See if we are a multi-node processor.
794 * All processors in the system have the same number of nodes
795 */
796 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
797 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
798 /* Single-node */
799 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
800 coreidsz);
801 cpi->cpi_chipid = cpi->cpi_procnodeid;
802 } else {
803
804 /*
805 * Multi-node revision D (2 nodes per package
806 * are supported)
807 */
808 cpi->cpi_procnodes_per_pkg = 2;
809
810 first_half = (cpi->cpi_pkgcoreid <=
811 (cpi->cpi_ncore_per_chip/2 - 1));
812
813 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
814 /* We are BSP */
815 cpi->cpi_procnodeid = (first_half ? 0 : 1);
816 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
817 } else {
818
819 /* We are AP */
820 /* NodeId[2:1] bits to use for reading F3xe8 */
821 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
822
823 nb_caps_reg =
824 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
825
826 /*
827 * Check IntNodeNum bit (31:30, but bit 31 is
828 * always 0 on dual-node processors)
829 */
830 if (BITX(nb_caps_reg, 30, 30) == 0)
831 cpi->cpi_procnodeid = node2_1 +
832 !first_half;
833 else
834 cpi->cpi_procnodeid = node2_1 +
835 first_half;
836
837 cpi->cpi_chipid = cpi->cpi_procnodeid >> 1;
838 }
839 }
840 } else if (cpi->cpi_family >= 0x11) {
841 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
842 cpi->cpi_chipid = cpi->cpi_procnodeid;
843 } else {
844 cpi->cpi_procnodeid = 0;
845 cpi->cpi_chipid = cpi->cpi_procnodeid;
846 }
847 }
848
849 /*
850 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
851 */
852 void
853 setup_xfem(void)
854 {
855 uint64_t flags = XFEATURE_LEGACY_FP;
856
857 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
858
859 if (is_x86_feature(x86_featureset, X86FSET_SSE))
860 flags |= XFEATURE_SSE;
861
862 if (is_x86_feature(x86_featureset, X86FSET_AVX))
863 flags |= XFEATURE_AVX;
864
865 set_xcr(XFEATURE_ENABLED_MASK, flags);
866
1420 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1421 add_x86_feature(featureset, X86FSET_ASYSC);
1422 }
1423
1424 /*
1425 * While we're thinking about system calls, note
1426 * that AMD processors don't support sysenter
1427 * in long mode at all, so don't try to program them.
1428 */
1429 if (x86_vendor == X86_VENDOR_AMD) {
1430 remove_x86_feature(featureset, X86FSET_SEP);
1431 }
1432 #endif
1433 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1434 add_x86_feature(featureset, X86FSET_TSCP);
1435 }
1436
1437 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1438 add_x86_feature(featureset, X86FSET_SVM);
1439 }
1440 break;
1441 default:
1442 break;
1443 }
1444
1445 /*
1446 * Get CPUID data about processor cores and hyperthreads.
1447 */
1448 switch (cpi->cpi_vendor) {
1449 case X86_VENDOR_Intel:
1450 if (cpi->cpi_maxeax >= 4) {
1451 cp = &cpi->cpi_std[4];
1452 cp->cp_eax = 4;
1453 cp->cp_ecx = 0;
1454 (void) __cpuid_insn(cp);
1455 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1456 }
1457 /*FALLTHROUGH*/
1458 case X86_VENDOR_AMD:
1459 if (cpi->cpi_xmaxeax < 0x80000008)
1528 cpi->cpi_ncore_per_chip = 1;
1529 }
1530
1531 /*
1532 * If more than one core, then this processor is CMP.
1533 */
1534 if (cpi->cpi_ncore_per_chip > 1) {
1535 add_x86_feature(featureset, X86FSET_CMP);
1536 }
1537
1538 /*
1539 * If the number of cores is the same as the number
1540 * of CPUs, then we cannot have HyperThreading.
1541 */
1542 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1543 remove_x86_feature(featureset, X86FSET_HTT);
1544 }
1545
1546 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1547 cpi->cpi_procnodes_per_pkg = 1;
1548 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1549 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1550 /*
1551 * Single-core single-threaded processors.
1552 */
1553 cpi->cpi_chipid = -1;
1554 cpi->cpi_clogid = 0;
1555 cpi->cpi_coreid = cpu->cpu_id;
1556 cpi->cpi_pkgcoreid = 0;
1557 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1558 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1559 else
1560 cpi->cpi_procnodeid = cpi->cpi_chipid;
1561 } else if (cpi->cpi_ncpu_per_chip > 1) {
1562 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1563 cpuid_intel_getids(cpu, featureset);
1564 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1565 cpuid_amd_getids(cpu);
1566 else {
1567 /*
1568 * All other processors are currently
1569 * assumed to have single cores.
1570 */
1571 cpi->cpi_coreid = cpi->cpi_chipid;
1572 cpi->cpi_pkgcoreid = 0;
1573 cpi->cpi_procnodeid = cpi->cpi_chipid;
1574 }
1575 }
1576
1577 /*
1578 * Synthesize chip "revision" and socket type
1579 */
1580 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1581 cpi->cpi_model, cpi->cpi_step);
1582 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1583 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1584 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1585 cpi->cpi_model, cpi->cpi_step);
1586
1587 pass1_done:
1588 cpi->cpi_pass = 1;
1589 }
1590
1591 /*
1592 * Make copies of the cpuid table entries we depend on, in
1593 * part for ease of parsing now, in part so that we have only
2987 cpuid_get_cacheid(cpu_t *cpu)
2988 {
2989 ASSERT(cpuid_checkpass(cpu, 1));
2990 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
2991 }
2992
2993 uint_t
2994 cpuid_get_procnodeid(cpu_t *cpu)
2995 {
2996 ASSERT(cpuid_checkpass(cpu, 1));
2997 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
2998 }
2999
3000 uint_t
3001 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3002 {
3003 ASSERT(cpuid_checkpass(cpu, 1));
3004 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3005 }
3006
3007 /*ARGSUSED*/
3008 int
3009 cpuid_have_cr8access(cpu_t *cpu)
3010 {
3011 #if defined(__amd64)
3012 return (1);
3013 #else
3014 struct cpuid_info *cpi;
3015
3016 ASSERT(cpu != NULL);
3017 cpi = cpu->cpu_m.mcpu_cpi;
3018 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3019 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3020 return (1);
3021 return (0);
3022 #endif
3023 }
3024
3025 uint32_t
3026 cpuid_get_apicid(cpu_t *cpu)
|
143 "asysc",
144 "nx",
145 "sse3",
146 "cx16",
147 "cmp",
148 "tscp",
149 "mwait",
150 "sse4a",
151 "cpuid",
152 "ssse3",
153 "sse4_1",
154 "sse4_2",
155 "1gpg",
156 "clfsh",
157 "64",
158 "aes",
159 "pclmulqdq",
160 "xsave",
161 "avx",
162 "vmx",
163 "svm",
164 "topoext"
165 };
166
167 boolean_t
168 is_x86_feature(void *featureset, uint_t feature)
169 {
170 ASSERT(feature < NUM_X86_FEATURES);
171 return (BT_TEST((ulong_t *)featureset, feature));
172 }
173
174 void
175 add_x86_feature(void *featureset, uint_t feature)
176 {
177 ASSERT(feature < NUM_X86_FEATURES);
178 BT_SET((ulong_t *)featureset, feature);
179 }
180
181 void
182 remove_x86_feature(void *featureset, uint_t feature)
183 {
184 ASSERT(feature < NUM_X86_FEATURES);
253 * Note: the kernel will use the maximum size required for all hardware
254 * features. It is not optimize for potential memory savings if features at
255 * the end of the save area are not enabled.
256 */
257 struct xsave_info {
258 uint32_t xsav_hw_features_low; /* Supported HW features */
259 uint32_t xsav_hw_features_high; /* Supported HW features */
260 size_t xsav_max_size; /* max size save area for HW features */
261 size_t ymm_size; /* AVX: size of ymm save area */
262 size_t ymm_offset; /* AVX: offset for ymm save area */
263 };
264
265
266 /*
267 * These constants determine how many of the elements of the
268 * cpuid we cache in the cpuid_info data structure; the
269 * remaining elements are accessible via the cpuid instruction.
270 */
271
272 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
273 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
274
275 /*
276 * Some terminology needs to be explained:
277 * - Socket: Something that can be plugged into a motherboard.
278 * - Package: Same as socket
279 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
280 * differently: there, chip is the same as processor node (below)
281 * - Processor node: Some AMD processors have more than one
282 * "subprocessor" embedded in a package. These subprocessors (nodes)
283 * are fully-functional processors themselves with cores, caches,
284 * memory controllers, PCI configuration spaces. They are connected
285 * inside the package with Hypertransport links. On single-node
286 * processors, processor node is equivalent to chip/socket/package.
287 * - Compute Unit: Some AMD processors pair cores in "compute units" that
288 * share the FPU and the I$ and L2 caches.
289 */
290
291 struct cpuid_info {
292 uint_t cpi_pass; /* last pass completed */
293 /*
294 * standard function information
295 */
296 uint_t cpi_maxeax; /* fn 0: %eax */
297 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
298 uint_t cpi_vendor; /* enum of cpi_vendorstr */
299
300 uint_t cpi_family; /* fn 1: extended family */
301 uint_t cpi_model; /* fn 1: extended model */
302 uint_t cpi_step; /* fn 1: stepping */
303 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
304 /* AMD: package/socket # */
305 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
306 int cpi_clogid; /* fn 1: %ebx: thread # */
307 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
308 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
329 * supported feature information
330 */
331 uint32_t cpi_support[5];
332 #define STD_EDX_FEATURES 0
333 #define AMD_EDX_FEATURES 1
334 #define TM_EDX_FEATURES 2
335 #define STD_ECX_FEATURES 3
336 #define AMD_ECX_FEATURES 4
337 /*
338 * Synthesized information, where known.
339 */
340 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
341 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
342 uint32_t cpi_socket; /* Chip package/socket type */
343
344 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
345 uint32_t cpi_apicid;
346 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
347 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
348 /* Intel: 1 */
349 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
350 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
351
352 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
353 };
354
355
356 static struct cpuid_info cpuid_info0;
357
358 /*
359 * These bit fields are defined by the Intel Application Note AP-485
360 * "Intel Processor Identification and the CPUID Instruction"
361 */
362 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
363 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
364 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
365 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
366 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
367 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
368
369 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
370 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
715 * Where the number of bits necessary to
716 * represent MC and HT fields together equals
717 * to the minimum number of bits necessary to
718 * store the value of cpi->cpi_ncpu_per_chip.
719 * Of those bits, the MC part uses the number
720 * of bits necessary to store the value of
721 * cpi->cpi_ncore_per_chip.
722 */
723 for (i = 1; i < ncpu_per_core; i <<= 1)
724 coreid_shift++;
725 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
726 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
727 } else if (is_x86_feature(feature, X86FSET_HTT)) {
728 /*
729 * Single-core multi-threaded processors.
730 */
731 cpi->cpi_coreid = cpi->cpi_chipid;
732 cpi->cpi_pkgcoreid = 0;
733 }
734 cpi->cpi_procnodeid = cpi->cpi_chipid;
735 cpi->cpi_compunitid = cpi->cpi_coreid;
736 }
737
738 static void
739 cpuid_amd_getids(cpu_t *cpu)
740 {
741 int i, first_half, coreidsz;
742 uint32_t nb_caps_reg;
743 uint_t node2_1;
744 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
745 struct cpuid_regs *cp;
746
747 /*
748 * AMD CMP chips currently have a single thread per core.
749 *
750 * Since no two cpus share a core we must assign a distinct coreid
751 * per cpu, and we do this by using the cpu_id. This scheme does not,
752 * however, guarantee that sibling cores of a chip will have sequential
753 * coreids starting at a multiple of the number of cores per chip -
754 * that is usually the case, but if the ACPI MADT table is presented
755 * in a different order then we need to perform a few more gymnastics
756 * for the pkgcoreid.
757 *
758 * All processors in the system have the same number of enabled
759 * cores. Cores within a processor are always numbered sequentially
760 * from 0 regardless of how many or which are disabled, and there
761 * is no way for operating system to discover the real core id when some
762 * are disabled.
763 *
764 * In family 0x15, the cores come in pairs called compute units. They
765 * share I$ and L2 caches and the FPU. Enumeration of this feature is
766 * simplified by the new topology extensions CPUID leaf, indicated by
767 * the X86 feature X86FSET_TOPOEXT.
768 */
769
770 cpi->cpi_coreid = cpu->cpu_id;
771 cpi->cpi_compunitid = cpu->cpu_id;
772
773 if (cpi->cpi_xmaxeax >= 0x80000008) {
774
775 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
776
777 /*
778 * In AMD parlance chip is really a node while Solaris
779 * sees chip as equivalent to socket/package.
780 */
781 cpi->cpi_ncore_per_chip =
782 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
783 if (coreidsz == 0) {
784 /* Use legacy method */
785 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
786 coreidsz++;
787 if (coreidsz == 0)
788 coreidsz = 1;
789 }
790 } else {
791 /* Assume single-core part */
792 cpi->cpi_ncore_per_chip = 1;
793 coreidsz = 1;
794 }
795
796 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
797 cpi->cpi_apicid & ((1<<coreidsz) - 1);
798 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
799
800 /* Get node ID, compute unit ID */
801 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
802 cpi->cpi_xmaxeax >= 0x8000001e) {
803 cp = &cpi->cpi_extd[0x1e];
804 cp->cp_eax = 0x8000001e;
805 (void) __cpuid_insn(cp);
806
807 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
808 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
809 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
810 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
811 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
812 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
813 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
814 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
815 } else if (cpi->cpi_family == 0x10) {
816 /*
817 * See if we are a multi-node processor.
818 * All processors in the system have the same number of nodes
819 */
820 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
821 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
822 /* Single-node */
823 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
824 coreidsz);
825 } else {
826
827 /*
828 * Multi-node revision D (2 nodes per package
829 * are supported)
830 */
831 cpi->cpi_procnodes_per_pkg = 2;
832
833 first_half = (cpi->cpi_pkgcoreid <=
834 (cpi->cpi_ncore_per_chip/2 - 1));
835
836 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
837 /* We are BSP */
838 cpi->cpi_procnodeid = (first_half ? 0 : 1);
839 } else {
840
841 /* We are AP */
842 /* NodeId[2:1] bits to use for reading F3xe8 */
843 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
844
845 nb_caps_reg =
846 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
847
848 /*
849 * Check IntNodeNum bit (31:30, but bit 31 is
850 * always 0 on dual-node processors)
851 */
852 if (BITX(nb_caps_reg, 30, 30) == 0)
853 cpi->cpi_procnodeid = node2_1 +
854 !first_half;
855 else
856 cpi->cpi_procnodeid = node2_1 +
857 first_half;
858 }
859 }
860 } else {
861 cpi->cpi_procnodeid = 0;
862 }
863
864 cpi->cpi_chipid =
865 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
866 }
867
868 /*
869 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
870 */
871 void
872 setup_xfem(void)
873 {
874 uint64_t flags = XFEATURE_LEGACY_FP;
875
876 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
877
878 if (is_x86_feature(x86_featureset, X86FSET_SSE))
879 flags |= XFEATURE_SSE;
880
881 if (is_x86_feature(x86_featureset, X86FSET_AVX))
882 flags |= XFEATURE_AVX;
883
884 set_xcr(XFEATURE_ENABLED_MASK, flags);
885
1439 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1440 add_x86_feature(featureset, X86FSET_ASYSC);
1441 }
1442
1443 /*
1444 * While we're thinking about system calls, note
1445 * that AMD processors don't support sysenter
1446 * in long mode at all, so don't try to program them.
1447 */
1448 if (x86_vendor == X86_VENDOR_AMD) {
1449 remove_x86_feature(featureset, X86FSET_SEP);
1450 }
1451 #endif
1452 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1453 add_x86_feature(featureset, X86FSET_TSCP);
1454 }
1455
1456 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1457 add_x86_feature(featureset, X86FSET_SVM);
1458 }
1459
1460 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1461 add_x86_feature(featureset, X86FSET_TOPOEXT);
1462 }
1463 break;
1464 default:
1465 break;
1466 }
1467
1468 /*
1469 * Get CPUID data about processor cores and hyperthreads.
1470 */
1471 switch (cpi->cpi_vendor) {
1472 case X86_VENDOR_Intel:
1473 if (cpi->cpi_maxeax >= 4) {
1474 cp = &cpi->cpi_std[4];
1475 cp->cp_eax = 4;
1476 cp->cp_ecx = 0;
1477 (void) __cpuid_insn(cp);
1478 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1479 }
1480 /*FALLTHROUGH*/
1481 case X86_VENDOR_AMD:
1482 if (cpi->cpi_xmaxeax < 0x80000008)
1551 cpi->cpi_ncore_per_chip = 1;
1552 }
1553
1554 /*
1555 * If more than one core, then this processor is CMP.
1556 */
1557 if (cpi->cpi_ncore_per_chip > 1) {
1558 add_x86_feature(featureset, X86FSET_CMP);
1559 }
1560
1561 /*
1562 * If the number of cores is the same as the number
1563 * of CPUs, then we cannot have HyperThreading.
1564 */
1565 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1566 remove_x86_feature(featureset, X86FSET_HTT);
1567 }
1568
1569 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1570 cpi->cpi_procnodes_per_pkg = 1;
1571 cpi->cpi_cores_per_compunit = 1;
1572 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1573 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1574 /*
1575 * Single-core single-threaded processors.
1576 */
1577 cpi->cpi_chipid = -1;
1578 cpi->cpi_clogid = 0;
1579 cpi->cpi_coreid = cpu->cpu_id;
1580 cpi->cpi_pkgcoreid = 0;
1581 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1582 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1583 else
1584 cpi->cpi_procnodeid = cpi->cpi_chipid;
1585 } else if (cpi->cpi_ncpu_per_chip > 1) {
1586 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1587 cpuid_intel_getids(cpu, featureset);
1588 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1589 cpuid_amd_getids(cpu);
1590 else {
1591 /*
1592 * All other processors are currently
1593 * assumed to have single cores.
1594 */
1595 cpi->cpi_coreid = cpi->cpi_chipid;
1596 cpi->cpi_pkgcoreid = 0;
1597 cpi->cpi_procnodeid = cpi->cpi_chipid;
1598 cpi->cpi_compunitid = cpi->cpi_chipid;
1599 }
1600 }
1601
1602 /*
1603 * Synthesize chip "revision" and socket type
1604 */
1605 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1606 cpi->cpi_model, cpi->cpi_step);
1607 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1608 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1609 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1610 cpi->cpi_model, cpi->cpi_step);
1611
1612 pass1_done:
1613 cpi->cpi_pass = 1;
1614 }
1615
1616 /*
1617 * Make copies of the cpuid table entries we depend on, in
1618 * part for ease of parsing now, in part so that we have only
3012 cpuid_get_cacheid(cpu_t *cpu)
3013 {
3014 ASSERT(cpuid_checkpass(cpu, 1));
3015 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3016 }
3017
3018 uint_t
3019 cpuid_get_procnodeid(cpu_t *cpu)
3020 {
3021 ASSERT(cpuid_checkpass(cpu, 1));
3022 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3023 }
3024
3025 uint_t
3026 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3027 {
3028 ASSERT(cpuid_checkpass(cpu, 1));
3029 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3030 }
3031
3032 uint_t
3033 cpuid_get_compunitid(cpu_t *cpu)
3034 {
3035 ASSERT(cpuid_checkpass(cpu, 1));
3036 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3037 }
3038
3039 uint_t
3040 cpuid_get_cores_per_compunit(cpu_t *cpu)
3041 {
3042 ASSERT(cpuid_checkpass(cpu, 1));
3043 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3044 }
3045
3046 /*ARGSUSED*/
3047 int
3048 cpuid_have_cr8access(cpu_t *cpu)
3049 {
3050 #if defined(__amd64)
3051 return (1);
3052 #else
3053 struct cpuid_info *cpi;
3054
3055 ASSERT(cpu != NULL);
3056 cpi = cpu->cpu_m.mcpu_cpi;
3057 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3058 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3059 return (1);
3060 return (0);
3061 #endif
3062 }
3063
3064 uint32_t
3065 cpuid_get_apicid(cpu_t *cpu)
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