2650 AMD family 0x15 PG support

@@ -243,10 +243,15 @@
                          */
                         return (1);
                 } else {
                         return (0);
                 }
+        case PGHW_FPU:
+                if (cpuid_get_cores_per_compunit(cp) > 1)
+                        return (1);
+                else
+                        return (0);
         case PGHW_PROCNODE:
                 if (cpuid_get_procnodes_per_pkg(cp) > 1)
                         return (1);
                 else
                         return (0);

@@ -304,10 +309,12 @@
         switch (hw) {
         case PGHW_IPIPE:
                 return (cpuid_get_coreid(cpu));
         case PGHW_CACHE:
                 return (cpuid_get_last_lvl_cacheid(cpu));
+        case PGHW_FPU:
+                return (cpuid_get_compunitid(cpu));
         case PGHW_PROCNODE:
                 return (cpuid_get_procnodeid(cpu));
         case PGHW_CHIP:
                 return (cpuid_get_chipid(cpu));
         case PGHW_POW_ACTIVE:

@@ -329,10 +336,11 @@
         int i, rank1, rank2;
 
         static pghw_type_t hw_hier[] = {
                 PGHW_IPIPE,
                 PGHW_CACHE,
+                PGHW_FPU,
                 PGHW_PROCNODE,
                 PGHW_CHIP,
                 PGHW_POW_IDLE,
                 PGHW_POW_ACTIVE,
                 PGHW_NUM_COMPONENTS

@@ -359,12 +367,17 @@
 pg_plat_cmt_policy(pghw_type_t hw)
 {
         /*
          * For shared caches, also load balance across them to
          * maximize aggregate cache capacity
+         *
+         * On AMD family 0x15 CPUs, cores come in pairs called
+         * compute units, sharing the FPU and the I$ and L2
+         * caches. Use balancing and cache affinity.
          */
         switch (hw) {
+        case PGHW_FPU:
         case PGHW_CACHE:
                 return (CMT_BALANCE|CMT_AFFINITY);
         default:
                 return (CMT_NO_POLICY);
         }