170 "\20" \
171 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
172 "\30mmx\27mmxext\25nx\22pse\21pat" \
173 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
174 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
175
176 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
177 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
178 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
179 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
180 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
181 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
182 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
183 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
184 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
185 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
186 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
187 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
188 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
189 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
190
191 #define FMT_CPUID_AMD_ECX \
192 "\20" \
193 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
194 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
195
196 /*
197 * Intel now seems to have claimed part of the "extended" function
198 * space that we previously for non-Intel implementors to use.
199 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
200 * is available in long mode i.e. what AMD indicate using bit 0.
201 * On the other hand, everything else is labelled as reserved.
202 */
203 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
204
205
206 #define P5_MCHADDR 0x0
207 #define P5_CESR 0x11
208 #define P5_CTR0 0x12
209 #define P5_CTR1 0x13
210
211 #define K5_MCHADDR 0x0
212 #define K5_MCHTYPE 0x01
351 #define X86FSET_NX 17
352 #define X86FSET_SSE3 18
353 #define X86FSET_CX16 19
354 #define X86FSET_CMP 20
355 #define X86FSET_TSCP 21
356 #define X86FSET_MWAIT 22
357 #define X86FSET_SSE4A 23
358 #define X86FSET_CPUID 24
359 #define X86FSET_SSSE3 25
360 #define X86FSET_SSE4_1 26
361 #define X86FSET_SSE4_2 27
362 #define X86FSET_1GPG 28
363 #define X86FSET_CLFSH 29
364 #define X86FSET_64 30
365 #define X86FSET_AES 31
366 #define X86FSET_PCLMULQDQ 32
367 #define X86FSET_XSAVE 33
368 #define X86FSET_AVX 34
369 #define X86FSET_VMX 35
370 #define X86FSET_SVM 36
371
372 /*
373 * flags to patch tsc_read routine.
374 */
375 #define X86_NO_TSC 0x0
376 #define X86_HAVE_TSCP 0x1
377 #define X86_TSC_MFENCE 0x2
378 #define X86_TSC_LFENCE 0x4
379
380 /*
381 * Intel Deep C-State invariant TSC in leaf 0x80000007.
382 */
383 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
384
385 /*
386 * Intel Deep C-state always-running local APIC timer
387 */
388 #define CPUID_CSTATE_ARAT (0x4)
389
390 /*
574 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
575
576 /*
577 * xgetbv/xsetbv support
578 */
579
580 #define XFEATURE_ENABLED_MASK 0x0
581 /*
582 * XFEATURE_ENABLED_MASK values (eax)
583 */
584 #define XFEATURE_LEGACY_FP 0x1
585 #define XFEATURE_SSE 0x2
586 #define XFEATURE_AVX 0x4
587 #define XFEATURE_MAX XFEATURE_AVX
588 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
589
590 #if !defined(_ASM)
591
592 #if defined(_KERNEL) || defined(_KMEMUSER)
593
594 #define NUM_X86_FEATURES 37
595 extern uchar_t x86_featureset[];
596
597 extern void free_x86_featureset(void *featureset);
598 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
599 extern void add_x86_feature(void *featureset, uint_t feature);
600 extern void remove_x86_feature(void *featureset, uint_t feature);
601 extern boolean_t compare_x86_featureset(void *setA, void *setB);
602 extern void print_x86_featureset(void *featureset);
603
604
605 extern uint_t x86_type;
606 extern uint_t x86_vendor;
607 extern uint_t x86_clflush_size;
608
609 extern uint_t pentiumpro_bug4046376;
610 extern uint_t pentiumpro_bug4064495;
611
612 extern uint_t enable486;
613
614 extern const char CyrixInstead[];
659 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
660 extern int cpuid_getidstr(struct cpu *, char *, size_t);
661 extern const char *cpuid_getvendorstr(struct cpu *);
662 extern uint_t cpuid_getvendor(struct cpu *);
663 extern uint_t cpuid_getfamily(struct cpu *);
664 extern uint_t cpuid_getmodel(struct cpu *);
665 extern uint_t cpuid_getstep(struct cpu *);
666 extern uint_t cpuid_getsig(struct cpu *);
667 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
668 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
669 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
670 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
671 extern int cpuid_get_chipid(struct cpu *);
672 extern id_t cpuid_get_coreid(struct cpu *);
673 extern int cpuid_get_pkgcoreid(struct cpu *);
674 extern int cpuid_get_clogid(struct cpu *);
675 extern int cpuid_get_cacheid(struct cpu *);
676 extern uint32_t cpuid_get_apicid(struct cpu *);
677 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
678 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
679 extern int cpuid_is_cmt(struct cpu *);
680 extern int cpuid_syscall32_insn(struct cpu *);
681 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
682
683 extern uint32_t cpuid_getchiprev(struct cpu *);
684 extern const char *cpuid_getchiprevstr(struct cpu *);
685 extern uint32_t cpuid_getsockettype(struct cpu *);
686 extern const char *cpuid_getsocketstr(struct cpu *);
687
688 extern int cpuid_have_cr8access(struct cpu *);
689
690 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
691
692 struct cpuid_info;
693
694 extern void setx86isalist(void);
695 extern void cpuid_alloc_space(struct cpu *);
696 extern void cpuid_free_space(struct cpu *);
697 extern void cpuid_pass1(struct cpu *, uchar_t *);
698 extern void cpuid_pass2(struct cpu *);
|
170 "\20" \
171 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
172 "\30mmx\27mmxext\25nx\22pse\21pat" \
173 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
174 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
175
176 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
177 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
178 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
179 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
180 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
181 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
182 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
183 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
184 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
185 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
186 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
187 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
188 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
189 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
190 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
191
192 #define FMT_CPUID_AMD_ECX \
193 "\20" \
194 "\22topoext" \
195 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
196 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
197
198 /*
199 * Intel now seems to have claimed part of the "extended" function
200 * space that we previously for non-Intel implementors to use.
201 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
202 * is available in long mode i.e. what AMD indicate using bit 0.
203 * On the other hand, everything else is labelled as reserved.
204 */
205 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
206
207
208 #define P5_MCHADDR 0x0
209 #define P5_CESR 0x11
210 #define P5_CTR0 0x12
211 #define P5_CTR1 0x13
212
213 #define K5_MCHADDR 0x0
214 #define K5_MCHTYPE 0x01
353 #define X86FSET_NX 17
354 #define X86FSET_SSE3 18
355 #define X86FSET_CX16 19
356 #define X86FSET_CMP 20
357 #define X86FSET_TSCP 21
358 #define X86FSET_MWAIT 22
359 #define X86FSET_SSE4A 23
360 #define X86FSET_CPUID 24
361 #define X86FSET_SSSE3 25
362 #define X86FSET_SSE4_1 26
363 #define X86FSET_SSE4_2 27
364 #define X86FSET_1GPG 28
365 #define X86FSET_CLFSH 29
366 #define X86FSET_64 30
367 #define X86FSET_AES 31
368 #define X86FSET_PCLMULQDQ 32
369 #define X86FSET_XSAVE 33
370 #define X86FSET_AVX 34
371 #define X86FSET_VMX 35
372 #define X86FSET_SVM 36
373 #define X86FSET_TOPOEXT 37
374
375 /*
376 * flags to patch tsc_read routine.
377 */
378 #define X86_NO_TSC 0x0
379 #define X86_HAVE_TSCP 0x1
380 #define X86_TSC_MFENCE 0x2
381 #define X86_TSC_LFENCE 0x4
382
383 /*
384 * Intel Deep C-State invariant TSC in leaf 0x80000007.
385 */
386 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
387
388 /*
389 * Intel Deep C-state always-running local APIC timer
390 */
391 #define CPUID_CSTATE_ARAT (0x4)
392
393 /*
577 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
578
579 /*
580 * xgetbv/xsetbv support
581 */
582
583 #define XFEATURE_ENABLED_MASK 0x0
584 /*
585 * XFEATURE_ENABLED_MASK values (eax)
586 */
587 #define XFEATURE_LEGACY_FP 0x1
588 #define XFEATURE_SSE 0x2
589 #define XFEATURE_AVX 0x4
590 #define XFEATURE_MAX XFEATURE_AVX
591 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
592
593 #if !defined(_ASM)
594
595 #if defined(_KERNEL) || defined(_KMEMUSER)
596
597 #define NUM_X86_FEATURES 38
598 extern uchar_t x86_featureset[];
599
600 extern void free_x86_featureset(void *featureset);
601 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
602 extern void add_x86_feature(void *featureset, uint_t feature);
603 extern void remove_x86_feature(void *featureset, uint_t feature);
604 extern boolean_t compare_x86_featureset(void *setA, void *setB);
605 extern void print_x86_featureset(void *featureset);
606
607
608 extern uint_t x86_type;
609 extern uint_t x86_vendor;
610 extern uint_t x86_clflush_size;
611
612 extern uint_t pentiumpro_bug4046376;
613 extern uint_t pentiumpro_bug4064495;
614
615 extern uint_t enable486;
616
617 extern const char CyrixInstead[];
662 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
663 extern int cpuid_getidstr(struct cpu *, char *, size_t);
664 extern const char *cpuid_getvendorstr(struct cpu *);
665 extern uint_t cpuid_getvendor(struct cpu *);
666 extern uint_t cpuid_getfamily(struct cpu *);
667 extern uint_t cpuid_getmodel(struct cpu *);
668 extern uint_t cpuid_getstep(struct cpu *);
669 extern uint_t cpuid_getsig(struct cpu *);
670 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
671 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
672 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
673 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
674 extern int cpuid_get_chipid(struct cpu *);
675 extern id_t cpuid_get_coreid(struct cpu *);
676 extern int cpuid_get_pkgcoreid(struct cpu *);
677 extern int cpuid_get_clogid(struct cpu *);
678 extern int cpuid_get_cacheid(struct cpu *);
679 extern uint32_t cpuid_get_apicid(struct cpu *);
680 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
681 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
682 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
683 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
684 extern int cpuid_is_cmt(struct cpu *);
685 extern int cpuid_syscall32_insn(struct cpu *);
686 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
687
688 extern uint32_t cpuid_getchiprev(struct cpu *);
689 extern const char *cpuid_getchiprevstr(struct cpu *);
690 extern uint32_t cpuid_getsockettype(struct cpu *);
691 extern const char *cpuid_getsocketstr(struct cpu *);
692
693 extern int cpuid_have_cr8access(struct cpu *);
694
695 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
696
697 struct cpuid_info;
698
699 extern void setx86isalist(void);
700 extern void cpuid_alloc_space(struct cpu *);
701 extern void cpuid_free_space(struct cpu *);
702 extern void cpuid_pass1(struct cpu *, uchar_t *);
703 extern void cpuid_pass2(struct cpu *);
|