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2650 AMD family 0x15 PG support
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2011, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 #ifndef _SYS_X86_ARCHEXT_H
34 34 #define _SYS_X86_ARCHEXT_H
35 35
36 36 #if !defined(_ASM)
37 37 #include <sys/regset.h>
38 38 #include <sys/processor.h>
39 39 #include <vm/seg_enum.h>
40 40 #include <vm/page.h>
41 41 #endif /* _ASM */
42 42
43 43 #ifdef __cplusplus
44 44 extern "C" {
45 45 #endif
46 46
47 47 /*
48 48 * cpuid instruction feature flags in %edx (standard function 1)
49 49 */
50 50
51 51 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
52 52 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
53 53 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
54 54 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
55 55 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
56 56 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
57 57 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
58 58 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
59 59 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
60 60 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
61 61 /* 0x400 - reserved */
62 62 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
63 63 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
64 64 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
65 65 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
66 66 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
67 67 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
68 68 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
69 69 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
70 70 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
71 71 /* 0x100000 - reserved */
72 72 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
73 73 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
74 74 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
75 75 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
76 76 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
77 77 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
78 78 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
79 79 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
80 80 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
81 81 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
82 82 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
83 83
84 84 #define FMT_CPUID_INTC_EDX \
85 85 "\20" \
86 86 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
87 87 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
88 88 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
89 89 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
90 90
91 91 /*
92 92 * cpuid instruction feature flags in %ecx (standard function 1)
93 93 */
94 94
95 95 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
96 96 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
97 97 /* 0x00000004 - reserved */
98 98 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
99 99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
100 100 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
101 101 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
102 102 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
103 103 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
104 104 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
105 105 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
106 106 /* 0x00000800 - reserved */
107 107 /* 0x00001000 - reserved */
108 108 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
109 109 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
110 110 /* 0x00008000 - reserved */
111 111 /* 0x00010000 - reserved */
112 112 /* 0x00020000 - reserved */
113 113 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
114 114 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
115 115 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
116 116 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
117 117 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
118 118 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
119 119 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
120 120 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
121 121 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
122 122
123 123 #define FMT_CPUID_INTC_ECX \
124 124 "\20" \
125 125 "\35avx\34osxsav\33xsave" \
126 126 "\32aes" \
127 127 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
128 128 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
129 129 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
130 130
131 131 /*
132 132 * cpuid instruction feature flags in %edx (extended function 0x80000001)
133 133 */
134 134
135 135 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
136 136 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
137 137 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
138 138 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
139 139 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
140 140 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
141 141 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
142 142 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
143 143 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
144 144 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
145 145 /* 0x00000400 - sysc on K6m6 */
146 146 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
147 147 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
148 148 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
149 149 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
150 150 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
151 151 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
152 152 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
153 153 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
154 154 /* 0x00040000 - reserved */
155 155 /* 0x00080000 - reserved */
156 156 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
157 157 /* 0x00200000 - reserved */
158 158 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
159 159 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
160 160 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
161 161 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
162 162 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
163 163 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
164 164 /* 0x10000000 - reserved */
165 165 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
166 166 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
167 167 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
168 168
169 169 #define FMT_CPUID_AMD_EDX \
170 170 "\20" \
171 171 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
172 172 "\30mmx\27mmxext\25nx\22pse\21pat" \
173 173 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
174 174 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
175 175
176 176 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
177 177 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
178 178 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
179 179 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
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180 180 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
181 181 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
182 182 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
183 183 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
184 184 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
185 185 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
186 186 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
187 187 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
188 188 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
189 189 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
190 +#define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
190 191
191 192 #define FMT_CPUID_AMD_ECX \
192 193 "\20" \
194 + "\22topoext" \
193 195 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
194 196 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
195 197
196 198 /*
197 199 * Intel now seems to have claimed part of the "extended" function
198 200 * space that we previously for non-Intel implementors to use.
199 201 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
200 202 * is available in long mode i.e. what AMD indicate using bit 0.
201 203 * On the other hand, everything else is labelled as reserved.
202 204 */
203 205 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
204 206
205 207
206 208 #define P5_MCHADDR 0x0
207 209 #define P5_CESR 0x11
208 210 #define P5_CTR0 0x12
209 211 #define P5_CTR1 0x13
210 212
211 213 #define K5_MCHADDR 0x0
212 214 #define K5_MCHTYPE 0x01
213 215 #define K5_TSC 0x10
214 216 #define K5_TR12 0x12
215 217
216 218 #define REG_PAT 0x277
217 219
218 220 #define REG_MC0_CTL 0x400
219 221 #define REG_MC5_MISC 0x417
220 222 #define REG_PERFCTR0 0xc1
221 223 #define REG_PERFCTR1 0xc2
222 224
223 225 #define REG_PERFEVNT0 0x186
224 226 #define REG_PERFEVNT1 0x187
225 227
226 228 #define REG_TSC 0x10 /* timestamp counter */
227 229 #define REG_APIC_BASE_MSR 0x1b
228 230 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
229 231
230 232 #if !defined(__xpv)
231 233 /*
232 234 * AMD C1E
233 235 */
234 236 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
235 237 #define AMD_ACTONCMPHALT_SHIFT 27
236 238 #define AMD_ACTONCMPHALT_MASK 3
237 239 #endif
238 240
239 241 #define MSR_DEBUGCTL 0x1d9
240 242
241 243 #define DEBUGCTL_LBR 0x01
242 244 #define DEBUGCTL_BTF 0x02
243 245
244 246 /* Intel P6, AMD */
245 247 #define MSR_LBR_FROM 0x1db
246 248 #define MSR_LBR_TO 0x1dc
247 249 #define MSR_LEX_FROM 0x1dd
248 250 #define MSR_LEX_TO 0x1de
249 251
250 252 /* Intel P4 (pre-Prescott, non P4 M) */
251 253 #define MSR_P4_LBSTK_TOS 0x1da
252 254 #define MSR_P4_LBSTK_0 0x1db
253 255 #define MSR_P4_LBSTK_1 0x1dc
254 256 #define MSR_P4_LBSTK_2 0x1dd
255 257 #define MSR_P4_LBSTK_3 0x1de
256 258
257 259 /* Intel Pentium M */
258 260 #define MSR_P6M_LBSTK_TOS 0x1c9
259 261 #define MSR_P6M_LBSTK_0 0x040
260 262 #define MSR_P6M_LBSTK_1 0x041
261 263 #define MSR_P6M_LBSTK_2 0x042
262 264 #define MSR_P6M_LBSTK_3 0x043
263 265 #define MSR_P6M_LBSTK_4 0x044
264 266 #define MSR_P6M_LBSTK_5 0x045
265 267 #define MSR_P6M_LBSTK_6 0x046
266 268 #define MSR_P6M_LBSTK_7 0x047
267 269
268 270 /* Intel P4 (Prescott) */
269 271 #define MSR_PRP4_LBSTK_TOS 0x1da
270 272 #define MSR_PRP4_LBSTK_FROM_0 0x680
271 273 #define MSR_PRP4_LBSTK_FROM_1 0x681
272 274 #define MSR_PRP4_LBSTK_FROM_2 0x682
273 275 #define MSR_PRP4_LBSTK_FROM_3 0x683
274 276 #define MSR_PRP4_LBSTK_FROM_4 0x684
275 277 #define MSR_PRP4_LBSTK_FROM_5 0x685
276 278 #define MSR_PRP4_LBSTK_FROM_6 0x686
277 279 #define MSR_PRP4_LBSTK_FROM_7 0x687
278 280 #define MSR_PRP4_LBSTK_FROM_8 0x688
279 281 #define MSR_PRP4_LBSTK_FROM_9 0x689
280 282 #define MSR_PRP4_LBSTK_FROM_10 0x68a
281 283 #define MSR_PRP4_LBSTK_FROM_11 0x68b
282 284 #define MSR_PRP4_LBSTK_FROM_12 0x68c
283 285 #define MSR_PRP4_LBSTK_FROM_13 0x68d
284 286 #define MSR_PRP4_LBSTK_FROM_14 0x68e
285 287 #define MSR_PRP4_LBSTK_FROM_15 0x68f
286 288 #define MSR_PRP4_LBSTK_TO_0 0x6c0
287 289 #define MSR_PRP4_LBSTK_TO_1 0x6c1
288 290 #define MSR_PRP4_LBSTK_TO_2 0x6c2
289 291 #define MSR_PRP4_LBSTK_TO_3 0x6c3
290 292 #define MSR_PRP4_LBSTK_TO_4 0x6c4
291 293 #define MSR_PRP4_LBSTK_TO_5 0x6c5
292 294 #define MSR_PRP4_LBSTK_TO_6 0x6c6
293 295 #define MSR_PRP4_LBSTK_TO_7 0x6c7
294 296 #define MSR_PRP4_LBSTK_TO_8 0x6c8
295 297 #define MSR_PRP4_LBSTK_TO_9 0x6c9
296 298 #define MSR_PRP4_LBSTK_TO_10 0x6ca
297 299 #define MSR_PRP4_LBSTK_TO_11 0x6cb
298 300 #define MSR_PRP4_LBSTK_TO_12 0x6cc
299 301 #define MSR_PRP4_LBSTK_TO_13 0x6cd
300 302 #define MSR_PRP4_LBSTK_TO_14 0x6ce
301 303 #define MSR_PRP4_LBSTK_TO_15 0x6cf
302 304
303 305 #define MCI_CTL_VALUE 0xffffffff
304 306
305 307 #define MTRR_TYPE_UC 0
306 308 #define MTRR_TYPE_WC 1
307 309 #define MTRR_TYPE_WT 4
308 310 #define MTRR_TYPE_WP 5
309 311 #define MTRR_TYPE_WB 6
310 312 #define MTRR_TYPE_UC_ 7
311 313
312 314 /*
313 315 * For Solaris we set up the page attritubute table in the following way:
314 316 * PAT0 Write-Back
315 317 * PAT1 Write-Through
316 318 * PAT2 Unchacheable-
317 319 * PAT3 Uncacheable
318 320 * PAT4 Write-Back
319 321 * PAT5 Write-Through
320 322 * PAT6 Write-Combine
321 323 * PAT7 Uncacheable
322 324 * The only difference from h/w default is entry 6.
323 325 */
324 326 #define PAT_DEFAULT_ATTRIBUTE \
325 327 ((uint64_t)MTRR_TYPE_WB | \
326 328 ((uint64_t)MTRR_TYPE_WT << 8) | \
327 329 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
328 330 ((uint64_t)MTRR_TYPE_UC << 24) | \
329 331 ((uint64_t)MTRR_TYPE_WB << 32) | \
330 332 ((uint64_t)MTRR_TYPE_WT << 40) | \
331 333 ((uint64_t)MTRR_TYPE_WC << 48) | \
332 334 ((uint64_t)MTRR_TYPE_UC << 56))
333 335
334 336 #define X86FSET_LARGEPAGE 0
335 337 #define X86FSET_TSC 1
336 338 #define X86FSET_MSR 2
337 339 #define X86FSET_MTRR 3
338 340 #define X86FSET_PGE 4
339 341 #define X86FSET_DE 5
340 342 #define X86FSET_CMOV 6
341 343 #define X86FSET_MMX 7
342 344 #define X86FSET_MCA 8
343 345 #define X86FSET_PAE 9
344 346 #define X86FSET_CX8 10
345 347 #define X86FSET_PAT 11
346 348 #define X86FSET_SEP 12
347 349 #define X86FSET_SSE 13
348 350 #define X86FSET_SSE2 14
349 351 #define X86FSET_HTT 15
350 352 #define X86FSET_ASYSC 16
351 353 #define X86FSET_NX 17
352 354 #define X86FSET_SSE3 18
353 355 #define X86FSET_CX16 19
354 356 #define X86FSET_CMP 20
355 357 #define X86FSET_TSCP 21
356 358 #define X86FSET_MWAIT 22
357 359 #define X86FSET_SSE4A 23
358 360 #define X86FSET_CPUID 24
359 361 #define X86FSET_SSSE3 25
360 362 #define X86FSET_SSE4_1 26
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361 363 #define X86FSET_SSE4_2 27
362 364 #define X86FSET_1GPG 28
363 365 #define X86FSET_CLFSH 29
364 366 #define X86FSET_64 30
365 367 #define X86FSET_AES 31
366 368 #define X86FSET_PCLMULQDQ 32
367 369 #define X86FSET_XSAVE 33
368 370 #define X86FSET_AVX 34
369 371 #define X86FSET_VMX 35
370 372 #define X86FSET_SVM 36
373 +#define X86FSET_TOPOEXT 37
371 374
372 375 /*
373 376 * flags to patch tsc_read routine.
374 377 */
375 378 #define X86_NO_TSC 0x0
376 379 #define X86_HAVE_TSCP 0x1
377 380 #define X86_TSC_MFENCE 0x2
378 381 #define X86_TSC_LFENCE 0x4
379 382
380 383 /*
381 384 * Intel Deep C-State invariant TSC in leaf 0x80000007.
382 385 */
383 386 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
384 387
385 388 /*
386 389 * Intel Deep C-state always-running local APIC timer
387 390 */
388 391 #define CPUID_CSTATE_ARAT (0x4)
389 392
390 393 /*
391 394 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
392 395 */
393 396 #define CPUID_EPB_SUPPORT (1 << 3)
394 397
395 398 /*
396 399 * Intel TSC deadline timer
397 400 */
398 401 #define CPUID_DEADLINE_TSC (1 << 24)
399 402
400 403 /*
401 404 * x86_type is a legacy concept; this is supplanted
402 405 * for most purposes by x86_featureset; modern CPUs
403 406 * should be X86_TYPE_OTHER
404 407 */
405 408 #define X86_TYPE_OTHER 0
406 409 #define X86_TYPE_486 1
407 410 #define X86_TYPE_P5 2
408 411 #define X86_TYPE_P6 3
409 412 #define X86_TYPE_CYRIX_486 4
410 413 #define X86_TYPE_CYRIX_6x86L 5
411 414 #define X86_TYPE_CYRIX_6x86 6
412 415 #define X86_TYPE_CYRIX_GXm 7
413 416 #define X86_TYPE_CYRIX_6x86MX 8
414 417 #define X86_TYPE_CYRIX_MediaGX 9
415 418 #define X86_TYPE_CYRIX_MII 10
416 419 #define X86_TYPE_VIA_CYRIX_III 11
417 420 #define X86_TYPE_P4 12
418 421
419 422 /*
420 423 * x86_vendor allows us to select between
421 424 * implementation features and helps guide
422 425 * the interpretation of the cpuid instruction.
423 426 */
424 427 #define X86_VENDOR_Intel 0
425 428 #define X86_VENDORSTR_Intel "GenuineIntel"
426 429
427 430 #define X86_VENDOR_IntelClone 1
428 431
429 432 #define X86_VENDOR_AMD 2
430 433 #define X86_VENDORSTR_AMD "AuthenticAMD"
431 434
432 435 #define X86_VENDOR_Cyrix 3
433 436 #define X86_VENDORSTR_CYRIX "CyrixInstead"
434 437
435 438 #define X86_VENDOR_UMC 4
436 439 #define X86_VENDORSTR_UMC "UMC UMC UMC "
437 440
438 441 #define X86_VENDOR_NexGen 5
439 442 #define X86_VENDORSTR_NexGen "NexGenDriven"
440 443
441 444 #define X86_VENDOR_Centaur 6
442 445 #define X86_VENDORSTR_Centaur "CentaurHauls"
443 446
444 447 #define X86_VENDOR_Rise 7
445 448 #define X86_VENDORSTR_Rise "RiseRiseRise"
446 449
447 450 #define X86_VENDOR_SiS 8
448 451 #define X86_VENDORSTR_SiS "SiS SiS SiS "
449 452
450 453 #define X86_VENDOR_TM 9
451 454 #define X86_VENDORSTR_TM "GenuineTMx86"
452 455
453 456 #define X86_VENDOR_NSC 10
454 457 #define X86_VENDORSTR_NSC "Geode by NSC"
455 458
456 459 /*
457 460 * Vendor string max len + \0
458 461 */
459 462 #define X86_VENDOR_STRLEN 13
460 463
461 464 /*
462 465 * Some vendor/family/model/stepping ranges are commonly grouped under
463 466 * a single identifying banner by the vendor. The following encode
464 467 * that "revision" in a uint32_t with the 8 most significant bits
465 468 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
466 469 * family, and the remaining 16 typically forming a bitmask of revisions
467 470 * within that family with more significant bits indicating "later" revisions.
468 471 */
469 472
470 473 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
471 474 #define _X86_CHIPREV_VENDOR_SHIFT 24
472 475 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
473 476 #define _X86_CHIPREV_FAMILY_SHIFT 16
474 477 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
475 478
476 479 #define _X86_CHIPREV_VENDOR(x) \
477 480 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
478 481 #define _X86_CHIPREV_FAMILY(x) \
479 482 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
480 483 #define _X86_CHIPREV_REV(x) \
481 484 ((x) & _X86_CHIPREV_REV_MASK)
482 485
483 486 /* True if x matches in vendor and family and if x matches the given rev mask */
484 487 #define X86_CHIPREV_MATCH(x, mask) \
485 488 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
486 489 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
487 490 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
488 491
489 492 /* True if x matches in vendor and family, and rev is at least minx */
490 493 #define X86_CHIPREV_ATLEAST(x, minx) \
491 494 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
492 495 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
493 496 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
494 497
495 498 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
496 499 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
497 500 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
498 501
499 502 /* True if x matches in vendor, and family is at least minx */
500 503 #define X86_CHIPFAM_ATLEAST(x, minx) \
501 504 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
502 505 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
503 506
504 507 /* Revision default */
505 508 #define X86_CHIPREV_UNKNOWN 0x0
506 509
507 510 /*
508 511 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
509 512 * sufficiently different that we will distinguish them; in all other
510 513 * case we will identify the major revision.
511 514 */
512 515 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
513 516 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
514 517 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
515 518 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
516 519 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
517 520 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
518 521 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
519 522
520 523 /*
521 524 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
522 525 */
523 526 #define X86_CHIPREV_AMD_10_REV_A \
524 527 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
525 528 #define X86_CHIPREV_AMD_10_REV_B \
526 529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
527 530 #define X86_CHIPREV_AMD_10_REV_C \
528 531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
529 532 #define X86_CHIPREV_AMD_10_REV_D \
530 533 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
531 534
532 535 /*
533 536 * Definitions for AMD Family 0x11.
534 537 */
535 538 #define X86_CHIPREV_AMD_11 \
536 539 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001)
537 540
538 541
539 542 /*
540 543 * Various socket/package types, extended as the need to distinguish
541 544 * a new type arises. The top 8 byte identfies the vendor and the
542 545 * remaining 24 bits describe 24 socket types.
543 546 */
544 547
545 548 #define _X86_SOCKET_VENDOR_SHIFT 24
546 549 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
547 550 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
548 551 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
549 552
550 553 #define _X86_SOCKET_MKVAL(vendor, bitval) \
551 554 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
552 555
553 556 #define X86_SOCKET_MATCH(s, mask) \
554 557 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
555 558 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
556 559
557 560 #define X86_SOCKET_UNKNOWN 0x0
558 561 /*
559 562 * AMD socket types
560 563 */
561 564 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
562 565 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
563 566 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
564 567 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
565 568 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
566 569 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
567 570 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
568 571 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
569 572 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
570 573 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
571 574 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
572 575 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
573 576 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
574 577 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
575 578
576 579 /*
577 580 * xgetbv/xsetbv support
578 581 */
579 582
580 583 #define XFEATURE_ENABLED_MASK 0x0
581 584 /*
582 585 * XFEATURE_ENABLED_MASK values (eax)
583 586 */
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584 587 #define XFEATURE_LEGACY_FP 0x1
585 588 #define XFEATURE_SSE 0x2
586 589 #define XFEATURE_AVX 0x4
587 590 #define XFEATURE_MAX XFEATURE_AVX
588 591 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
589 592
590 593 #if !defined(_ASM)
591 594
592 595 #if defined(_KERNEL) || defined(_KMEMUSER)
593 596
594 -#define NUM_X86_FEATURES 37
597 +#define NUM_X86_FEATURES 38
595 598 extern uchar_t x86_featureset[];
596 599
597 600 extern void free_x86_featureset(void *featureset);
598 601 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
599 602 extern void add_x86_feature(void *featureset, uint_t feature);
600 603 extern void remove_x86_feature(void *featureset, uint_t feature);
601 604 extern boolean_t compare_x86_featureset(void *setA, void *setB);
602 605 extern void print_x86_featureset(void *featureset);
603 606
604 607
605 608 extern uint_t x86_type;
606 609 extern uint_t x86_vendor;
607 610 extern uint_t x86_clflush_size;
608 611
609 612 extern uint_t pentiumpro_bug4046376;
610 613 extern uint_t pentiumpro_bug4064495;
611 614
612 615 extern uint_t enable486;
613 616
614 617 extern const char CyrixInstead[];
615 618
616 619 #endif
617 620
618 621 #if defined(_KERNEL)
619 622
620 623 /*
621 624 * This structure is used to pass arguments and get return values back
622 625 * from the CPUID instruction in __cpuid_insn() routine.
623 626 */
624 627 struct cpuid_regs {
625 628 uint32_t cp_eax;
626 629 uint32_t cp_ebx;
627 630 uint32_t cp_ecx;
628 631 uint32_t cp_edx;
629 632 };
630 633
631 634 /*
632 635 * Utility functions to get/set extended control registers (XCR)
633 636 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
634 637 */
635 638 extern uint64_t get_xcr(uint_t);
636 639 extern void set_xcr(uint_t, uint64_t);
637 640
638 641 extern uint64_t rdmsr(uint_t);
639 642 extern void wrmsr(uint_t, const uint64_t);
640 643 extern uint64_t xrdmsr(uint_t);
641 644 extern void xwrmsr(uint_t, const uint64_t);
642 645 extern int checked_rdmsr(uint_t, uint64_t *);
643 646 extern int checked_wrmsr(uint_t, uint64_t);
644 647
645 648 extern void invalidate_cache(void);
646 649 extern ulong_t getcr4(void);
647 650 extern void setcr4(ulong_t);
648 651
649 652 extern void mtrr_sync(void);
650 653
651 654 extern void cpu_fast_syscall_enable(void *);
652 655 extern void cpu_fast_syscall_disable(void *);
653 656
654 657 struct cpu;
655 658
656 659 extern int cpuid_checkpass(struct cpu *, int);
657 660 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
658 661 extern uint32_t __cpuid_insn(struct cpuid_regs *);
659 662 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
660 663 extern int cpuid_getidstr(struct cpu *, char *, size_t);
661 664 extern const char *cpuid_getvendorstr(struct cpu *);
662 665 extern uint_t cpuid_getvendor(struct cpu *);
663 666 extern uint_t cpuid_getfamily(struct cpu *);
664 667 extern uint_t cpuid_getmodel(struct cpu *);
665 668 extern uint_t cpuid_getstep(struct cpu *);
666 669 extern uint_t cpuid_getsig(struct cpu *);
667 670 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
668 671 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
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669 672 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
670 673 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
671 674 extern int cpuid_get_chipid(struct cpu *);
672 675 extern id_t cpuid_get_coreid(struct cpu *);
673 676 extern int cpuid_get_pkgcoreid(struct cpu *);
674 677 extern int cpuid_get_clogid(struct cpu *);
675 678 extern int cpuid_get_cacheid(struct cpu *);
676 679 extern uint32_t cpuid_get_apicid(struct cpu *);
677 680 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
678 681 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
682 +extern uint_t cpuid_get_compunitid(struct cpu *cpu);
683 +extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
679 684 extern int cpuid_is_cmt(struct cpu *);
680 685 extern int cpuid_syscall32_insn(struct cpu *);
681 686 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
682 687
683 688 extern uint32_t cpuid_getchiprev(struct cpu *);
684 689 extern const char *cpuid_getchiprevstr(struct cpu *);
685 690 extern uint32_t cpuid_getsockettype(struct cpu *);
686 691 extern const char *cpuid_getsocketstr(struct cpu *);
687 692
688 693 extern int cpuid_have_cr8access(struct cpu *);
689 694
690 695 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
691 696
692 697 struct cpuid_info;
693 698
694 699 extern void setx86isalist(void);
695 700 extern void cpuid_alloc_space(struct cpu *);
696 701 extern void cpuid_free_space(struct cpu *);
697 702 extern void cpuid_pass1(struct cpu *, uchar_t *);
698 703 extern void cpuid_pass2(struct cpu *);
699 704 extern void cpuid_pass3(struct cpu *);
700 705 extern uint_t cpuid_pass4(struct cpu *);
701 706 extern void cpuid_set_cpu_properties(void *, processorid_t,
702 707 struct cpuid_info *);
703 708
704 709 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
705 710 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
706 711
707 712 #if !defined(__xpv)
708 713 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
709 714 extern void cpuid_mwait_free(struct cpu *);
710 715 extern int cpuid_deep_cstates_supported(void);
711 716 extern int cpuid_arat_supported(void);
712 717 extern int cpuid_iepb_supported(struct cpu *);
713 718 extern int cpuid_deadline_tsc_supported(void);
714 719 extern int vmware_platform(void);
715 720 #endif
716 721
717 722 struct cpu_ucode_info;
718 723
719 724 extern void ucode_alloc_space(struct cpu *);
720 725 extern void ucode_free_space(struct cpu *);
721 726 extern void ucode_check(struct cpu *);
722 727 extern void ucode_cleanup();
723 728
724 729 #if !defined(__xpv)
725 730 extern char _tsc_mfence_start;
726 731 extern char _tsc_mfence_end;
727 732 extern char _tscp_start;
728 733 extern char _tscp_end;
729 734 extern char _no_rdtsc_start;
730 735 extern char _no_rdtsc_end;
731 736 extern char _tsc_lfence_start;
732 737 extern char _tsc_lfence_end;
733 738 #endif
734 739
735 740 #if !defined(__xpv)
736 741 extern char bcopy_patch_start;
737 742 extern char bcopy_patch_end;
738 743 extern char bcopy_ck_size;
739 744 #endif
740 745
741 746 extern void post_startup_cpu_fixups(void);
742 747
743 748 extern uint_t workaround_errata(struct cpu *);
744 749
745 750 #if defined(OPTERON_ERRATUM_93)
746 751 extern int opteron_erratum_93;
747 752 #endif
748 753
749 754 #if defined(OPTERON_ERRATUM_91)
750 755 extern int opteron_erratum_91;
751 756 #endif
752 757
753 758 #if defined(OPTERON_ERRATUM_100)
754 759 extern int opteron_erratum_100;
755 760 #endif
756 761
757 762 #if defined(OPTERON_ERRATUM_121)
758 763 extern int opteron_erratum_121;
759 764 #endif
760 765
761 766 #if defined(OPTERON_WORKAROUND_6323525)
762 767 extern int opteron_workaround_6323525;
763 768 extern void patch_workaround_6323525(void);
764 769 #endif
765 770
766 771 #if !defined(__xpv)
767 772 extern void determine_platform(void);
768 773 #endif
769 774 extern int get_hwenv(void);
770 775 extern int is_controldom(void);
771 776
772 777 extern void xsave_setup_msr(struct cpu *);
773 778
774 779 /*
775 780 * Defined hardware environments
776 781 */
777 782 #define HW_NATIVE 0x00 /* Running on bare metal */
778 783 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */
779 784 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */
780 785 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */
781 786
782 787 #endif /* _KERNEL */
783 788
784 789 #endif
785 790
786 791 #ifdef __cplusplus
787 792 }
788 793 #endif
789 794
790 795 #endif /* _SYS_X86_ARCHEXT_H */
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