1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2017, Joyent, Inc. All rights reserved. 31 */ 32 33 /* 34 * To understand how the pcplusmp module interacts with the interrupt subsystem 35 * read the theory statement in uts/i86pc/os/intr.c. 36 */ 37 38 /* 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 42 * PSMI 1.5 extensions are supported in Solaris Nevada. 43 * PSMI 1.6 extensions are supported in Solaris Nevada. 44 * PSMI 1.7 extensions are supported in Solaris Nevada. 45 */ 46 #define PSMI_1_7 47 48 #include <sys/processor.h> 49 #include <sys/time.h> 50 #include <sys/psm.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/cram.h> 53 #include <sys/acpi/acpi.h> 54 #include <sys/acpica.h> 55 #include <sys/psm_common.h> 56 #include <sys/apic.h> 57 #include <sys/pit.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/ddi_impldefs.h> 61 #include <sys/pci.h> 62 #include <sys/promif.h> 63 #include <sys/x86_archext.h> 64 #include <sys/cpc_impl.h> 65 #include <sys/uadmin.h> 66 #include <sys/panic.h> 67 #include <sys/debug.h> 68 #include <sys/archsystm.h> 69 #include <sys/trap.h> 70 #include <sys/machsystm.h> 71 #include <sys/sysmacros.h> 72 #include <sys/cpuvar.h> 73 #include <sys/rm_platter.h> 74 #include <sys/privregs.h> 75 #include <sys/note.h> 76 #include <sys/pci_intr_lib.h> 77 #include <sys/spl.h> 78 #include <sys/clock.h> 79 #include <sys/cyclic.h> 80 #include <sys/dditypes.h> 81 #include <sys/sunddi.h> 82 #include <sys/x_call.h> 83 #include <sys/reboot.h> 84 #include <sys/hpet.h> 85 #include <sys/apic_common.h> 86 #include <sys/apic_timer.h> 87 88 /* 89 * Local Function Prototypes 90 */ 91 static void apic_init_intr(void); 92 93 /* 94 * standard MP entries 95 */ 96 static int apic_probe(void); 97 static int apic_getclkirq(int ipl); 98 static void apic_init(void); 99 static void apic_picinit(void); 100 static int apic_post_cpu_start(void); 101 static int apic_intr_enter(int ipl, int *vect); 102 static void apic_setspl(int ipl); 103 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 104 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 105 static int apic_disable_intr(processorid_t cpun); 106 static void apic_enable_intr(processorid_t cpun); 107 static int apic_get_ipivect(int ipl, int type); 108 static void apic_post_cyclic_setup(void *arg); 109 110 /* 111 * The following vector assignments influence the value of ipltopri and 112 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 113 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 114 * we care to do so in future. Note some IPLs which are rarely used 115 * will share the vector ranges and heavily used IPLs (5 and 6) have 116 * a wide range. 117 * 118 * This array is used to initialize apic_ipls[] (in apic_init()). 119 * 120 * IPL Vector range. as passed to intr_enter 121 * 0 none. 122 * 1,2,3 0x20-0x2f 0x0-0xf 123 * 4 0x30-0x3f 0x10-0x1f 124 * 5 0x40-0x5f 0x20-0x3f 125 * 6 0x60-0x7f 0x40-0x5f 126 * 7,8,9 0x80-0x8f 0x60-0x6f 127 * 10 0x90-0x9f 0x70-0x7f 128 * 11 0xa0-0xaf 0x80-0x8f 129 * ... ... 130 * 15 0xe0-0xef 0xc0-0xcf 131 * 15 0xf0-0xff 0xd0-0xdf 132 */ 133 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 134 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 135 }; 136 /* 137 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 138 * NOTE that this is vector as passed into intr_enter which is 139 * programmed vector - 0x20 (APIC_BASE_VECT) 140 */ 141 142 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 143 /* The taskpri to be programmed into apic to mask given ipl */ 144 145 /* 146 * Correlation of the hardware vector to the IPL in use, initialized 147 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 148 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 149 * connected to errata-stricken IOAPICs 150 */ 151 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 152 153 /* 154 * Patchable global variables. 155 */ 156 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 157 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 158 159 /* 160 * Local static data 161 */ 162 static struct psm_ops apic_ops = { 163 apic_probe, 164 165 apic_init, 166 apic_picinit, 167 apic_intr_enter, 168 apic_intr_exit, 169 apic_setspl, 170 apic_addspl, 171 apic_delspl, 172 apic_disable_intr, 173 apic_enable_intr, 174 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 175 (void (*)(int))NULL, /* psm_set_softintr */ 176 177 apic_set_idlecpu, 178 apic_unset_idlecpu, 179 180 apic_clkinit, 181 apic_getclkirq, 182 (void (*)(void))NULL, /* psm_hrtimeinit */ 183 apic_gethrtime, 184 185 apic_get_next_processorid, 186 apic_cpu_start, 187 apic_post_cpu_start, 188 apic_shutdown, 189 apic_get_ipivect, 190 apic_send_ipi, 191 192 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 193 (void (*)(int, char *))NULL, /* psm_notify_error */ 194 (void (*)(int))NULL, /* psm_notify_func */ 195 apic_timer_reprogram, 196 apic_timer_enable, 197 apic_timer_disable, 198 apic_post_cyclic_setup, 199 apic_preshutdown, 200 apic_intr_ops, /* Advanced DDI Interrupt framework */ 201 apic_state, /* save, restore apic state for S3 */ 202 apic_cpu_ops, /* CPU control interface. */ 203 }; 204 205 struct psm_ops *psmops = &apic_ops; 206 207 static struct psm_info apic_psm_info = { 208 PSM_INFO_VER01_7, /* version */ 209 PSM_OWN_EXCLUSIVE, /* ownership */ 210 (struct psm_ops *)&apic_ops, /* operation */ 211 APIC_PCPLUSMP_NAME, /* machine name */ 212 "pcplusmp v1.4 compatible", 213 }; 214 215 static void *apic_hdlp; 216 217 /* to gather intr data and redistribute */ 218 static void apic_redistribute_compute(void); 219 220 /* 221 * This is the loadable module wrapper 222 */ 223 224 int 225 _init(void) 226 { 227 if (apic_coarse_hrtime) 228 apic_ops.psm_gethrtime = &apic_gettime; 229 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 230 } 231 232 int 233 _fini(void) 234 { 235 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 236 } 237 238 int 239 _info(struct modinfo *modinfop) 240 { 241 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 242 } 243 244 static int 245 apic_probe(void) 246 { 247 /* check if apix is initialized */ 248 if (apix_enable && apix_loaded()) 249 return (PSM_FAILURE); 250 251 /* 252 * Check whether x2APIC mode was activated by BIOS. We don't support 253 * that in pcplusmp as apix normally handles that. 254 */ 255 if (apic_local_mode() == LOCAL_X2APIC) 256 return (PSM_FAILURE); 257 258 /* continue using pcplusmp PSM */ 259 apix_enable = 0; 260 261 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 262 } 263 264 static uchar_t 265 apic_xlate_vector_by_irq(uchar_t irq) 266 { 267 if (apic_irq_table[irq] == NULL) 268 return (0); 269 270 return (apic_irq_table[irq]->airq_vector); 271 } 272 273 void 274 apic_init(void) 275 { 276 int i; 277 int j = 1; 278 279 psm_get_ioapicid = apic_get_ioapicid; 280 psm_get_localapicid = apic_get_localapicid; 281 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 282 283 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 284 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 285 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 286 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 287 /* get to highest vector at the same ipl */ 288 continue; 289 for (; j <= apic_vectortoipl[i]; j++) { 290 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 291 APIC_BASE_VECT; 292 } 293 } 294 for (; j < MAXIPL + 1; j++) 295 /* fill up any empty ipltopri slots */ 296 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 297 apic_init_common(); 298 299 #if !defined(__amd64) 300 if (cpuid_have_cr8access(CPU)) 301 apic_have_32bit_cr8 = 1; 302 #endif 303 } 304 305 static void 306 apic_init_intr(void) 307 { 308 processorid_t cpun = psm_get_cpu_id(); 309 uint_t nlvt; 310 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 311 312 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 313 314 ASSERT(apic_mode == LOCAL_APIC); 315 316 /* 317 * We are running APIC in MMIO mode. 318 */ 319 if (apic_flat_model) { 320 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL); 321 } else { 322 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL); 323 } 324 325 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun); 326 327 if (apic_directed_EOI_supported()) { 328 /* 329 * Setting the 12th bit in the Spurious Interrupt Vector 330 * Register suppresses broadcast EOIs generated by the local 331 * APIC. The suppression of broadcast EOIs happens only when 332 * interrupts are level-triggered. 333 */ 334 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 335 } 336 337 /* need to enable APIC before unmasking NMI */ 338 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 339 340 /* 341 * Presence of an invalid vector with delivery mode AV_FIXED can 342 * cause an error interrupt, even if the entry is masked...so 343 * write a valid vector to LVT entries along with the mask bit 344 */ 345 346 /* All APICs have timer and LINT0/1 */ 347 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 348 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 349 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 350 351 /* 352 * On integrated APICs, the number of LVT entries is 353 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 354 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 355 */ 356 357 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 358 nlvt = 3; 359 } else { 360 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 361 0xFF) + 1; 362 } 363 364 if (nlvt >= 5) { 365 /* Enable performance counter overflow interrupt */ 366 367 if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 368 apic_enable_cpcovf_intr = 0; 369 if (apic_enable_cpcovf_intr) { 370 if (apic_cpcovf_vect == 0) { 371 int ipl = APIC_PCINT_IPL; 372 int irq = apic_get_ipivect(ipl, -1); 373 374 ASSERT(irq != -1); 375 apic_cpcovf_vect = 376 apic_irq_table[irq]->airq_vector; 377 ASSERT(apic_cpcovf_vect); 378 (void) add_avintr(NULL, ipl, 379 (avfunc)kcpc_hw_overflow_intr, 380 "apic pcint", irq, NULL, NULL, NULL, NULL); 381 kcpc_hw_overflow_intr_installed = 1; 382 kcpc_hw_enable_cpc_intr = 383 apic_cpcovf_mask_clear; 384 } 385 apic_reg_ops->apic_write(APIC_PCINT_VECT, 386 apic_cpcovf_vect); 387 } 388 } 389 390 if (nlvt >= 6) { 391 /* Only mask TM intr if the BIOS apparently doesn't use it */ 392 393 uint32_t lvtval; 394 395 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 396 if (((lvtval & AV_MASK) == AV_MASK) || 397 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 398 apic_reg_ops->apic_write(APIC_THERM_VECT, 399 AV_MASK|APIC_RESV_IRQ); 400 } 401 } 402 403 /* Enable error interrupt */ 404 405 if (nlvt >= 4 && apic_enable_error_intr) { 406 if (apic_errvect == 0) { 407 int ipl = 0xf; /* get highest priority intr */ 408 int irq = apic_get_ipivect(ipl, -1); 409 410 ASSERT(irq != -1); 411 apic_errvect = apic_irq_table[irq]->airq_vector; 412 ASSERT(apic_errvect); 413 /* 414 * Not PSMI compliant, but we are going to merge 415 * with ON anyway 416 */ 417 (void) add_avintr((void *)NULL, ipl, 418 (avfunc)apic_error_intr, "apic error intr", 419 irq, NULL, NULL, NULL, NULL); 420 } 421 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 422 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 423 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 424 } 425 426 /* Enable CMCI interrupt */ 427 if (cmi_enable_cmci) { 428 429 mutex_enter(&cmci_cpu_setup_lock); 430 if (cmci_cpu_setup_registered == 0) { 431 mutex_enter(&cpu_lock); 432 register_cpu_setup_func(cmci_cpu_setup, NULL); 433 mutex_exit(&cpu_lock); 434 cmci_cpu_setup_registered = 1; 435 } 436 mutex_exit(&cmci_cpu_setup_lock); 437 438 if (apic_cmci_vect == 0) { 439 int ipl = 0x2; 440 int irq = apic_get_ipivect(ipl, -1); 441 442 ASSERT(irq != -1); 443 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 444 ASSERT(apic_cmci_vect); 445 446 (void) add_avintr(NULL, ipl, 447 (avfunc)cmi_cmci_trap, 448 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 449 } 450 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 451 } 452 } 453 454 static void 455 apic_picinit(void) 456 { 457 int i, j; 458 uint_t isr; 459 460 /* 461 * Initialize and enable interrupt remapping before apic 462 * hardware initialization 463 */ 464 apic_intrmap_init(apic_mode); 465 466 /* 467 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 468 * bit on without clearing it with EOI. Since softint 469 * uses vector 0x20 to interrupt itself, so softint will 470 * not work on this machine. In order to fix this problem 471 * a check is made to verify all the isr bits are clear. 472 * If not, EOIs are issued to clear the bits. 473 */ 474 for (i = 7; i >= 1; i--) { 475 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 476 if (isr != 0) 477 for (j = 0; ((j < 32) && (isr != 0)); j++) 478 if (isr & (1 << j)) { 479 apic_reg_ops->apic_write( 480 APIC_EOI_REG, 0); 481 isr &= ~(1 << j); 482 apic_error |= APIC_ERR_BOOT_EOI; 483 } 484 } 485 486 /* set a flag so we know we have run apic_picinit() */ 487 apic_picinit_called = 1; 488 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 489 LOCK_INIT_CLEAR(&apic_ioapic_lock); 490 LOCK_INIT_CLEAR(&apic_error_lock); 491 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 492 493 picsetup(); /* initialise the 8259 */ 494 495 /* add nmi handler - least priority nmi handler */ 496 LOCK_INIT_CLEAR(&apic_nmi_lock); 497 498 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 499 "pcplusmp NMI handler", (caddr_t)NULL)) 500 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 501 502 /* 503 * Check for directed-EOI capability in the local APIC. 504 */ 505 if (apic_directed_EOI_supported() == 1) { 506 apic_set_directed_EOI_handler(); 507 } 508 509 apic_init_intr(); 510 511 /* enable apic mode if imcr present */ 512 if (apic_imcrp) { 513 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 514 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 515 } 516 517 ioapic_init_intr(IOAPIC_MASK); 518 } 519 520 #ifdef DEBUG 521 void 522 apic_break(void) 523 { 524 } 525 #endif /* DEBUG */ 526 527 /* 528 * platform_intr_enter 529 * 530 * Called at the beginning of the interrupt service routine to 531 * mask all level equal to and below the interrupt priority 532 * of the interrupting vector. An EOI should be given to 533 * the interrupt controller to enable other HW interrupts. 534 * 535 * Return -1 for spurious interrupts 536 * 537 */ 538 /*ARGSUSED*/ 539 static int 540 apic_intr_enter(int ipl, int *vectorp) 541 { 542 uchar_t vector; 543 int nipl; 544 int irq; 545 ulong_t iflag; 546 apic_cpus_info_t *cpu_infop; 547 548 /* 549 * The real vector delivered is (*vectorp + 0x20), but our caller 550 * subtracts 0x20 from the vector before passing it to us. 551 * (That's why APIC_BASE_VECT is 0x20.) 552 */ 553 vector = (uchar_t)*vectorp; 554 555 /* if interrupted by the clock, increment apic_nsec_since_boot */ 556 if (vector == apic_clkvect) { 557 if (!apic_oneshot) { 558 /* NOTE: this is not MT aware */ 559 apic_hrtime_stamp++; 560 apic_nsec_since_boot += apic_nsec_per_intr; 561 apic_hrtime_stamp++; 562 last_count_read = apic_hertz_count; 563 apic_redistribute_compute(); 564 } 565 566 /* We will avoid all the book keeping overhead for clock */ 567 nipl = apic_ipls[vector]; 568 569 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 570 571 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 572 apic_reg_ops->apic_send_eoi(0); 573 574 return (nipl); 575 } 576 577 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 578 579 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 580 cpu_infop->aci_spur_cnt++; 581 return (APIC_INT_SPURIOUS); 582 } 583 584 /* Check if the vector we got is really what we need */ 585 if (apic_revector_pending) { 586 /* 587 * Disable interrupts for the duration of 588 * the vector translation to prevent a self-race for 589 * the apic_revector_lock. This cannot be done 590 * in apic_xlate_vector because it is recursive and 591 * we want the vector translation to be atomic with 592 * respect to other (higher-priority) interrupts. 593 */ 594 iflag = intr_clear(); 595 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 596 APIC_BASE_VECT; 597 intr_restore(iflag); 598 } 599 600 nipl = apic_ipls[vector]; 601 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 602 603 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 604 605 cpu_infop->aci_current[nipl] = (uchar_t)irq; 606 cpu_infop->aci_curipl = (uchar_t)nipl; 607 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 608 609 /* 610 * apic_level_intr could have been assimilated into the irq struct. 611 * but, having it as a character array is more efficient in terms of 612 * cache usage. So, we leave it as is. 613 */ 614 if (!apic_level_intr[irq]) { 615 apic_reg_ops->apic_send_eoi(0); 616 } 617 618 #ifdef DEBUG 619 APIC_DEBUG_BUF_PUT(vector); 620 APIC_DEBUG_BUF_PUT(irq); 621 APIC_DEBUG_BUF_PUT(nipl); 622 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 623 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 624 drv_usecwait(apic_stretch_interrupts); 625 626 if (apic_break_on_cpu == psm_get_cpu_id()) 627 apic_break(); 628 #endif /* DEBUG */ 629 return (nipl); 630 } 631 632 void 633 apic_intr_exit(int prev_ipl, int irq) 634 { 635 apic_cpus_info_t *cpu_infop; 636 637 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]); 638 639 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 640 if (apic_level_intr[irq]) 641 apic_reg_ops->apic_send_eoi(irq); 642 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 643 /* ISR above current pri could not be in progress */ 644 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 645 } 646 647 intr_exit_fn_t 648 psm_intr_exit_fn(void) 649 { 650 return (apic_intr_exit); 651 } 652 653 /* 654 * Mask all interrupts below or equal to the given IPL. 655 */ 656 static void 657 apic_setspl(int ipl) 658 { 659 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]); 660 661 /* interrupts at ipl above this cannot be in progress */ 662 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 663 /* 664 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 665 * have enough time to come in before the priority is raised again 666 * during the idle() loop. 667 */ 668 if (apic_setspl_delay) 669 (void) apic_reg_ops->apic_get_pri(); 670 } 671 672 /*ARGSUSED*/ 673 static int 674 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 675 { 676 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 677 } 678 679 static int 680 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 681 { 682 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 683 } 684 685 static int 686 apic_post_cpu_start(void) 687 { 688 int cpun; 689 static int cpus_started = 1; 690 691 /* We know this CPU + BSP started successfully. */ 692 cpus_started++; 693 694 splx(ipltospl(LOCK_LEVEL)); 695 apic_init_intr(); 696 697 /* 698 * since some systems don't enable the internal cache on the non-boot 699 * cpus, so we have to enable them here 700 */ 701 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 702 703 APIC_AV_PENDING_SET(); 704 705 /* 706 * We may be booting, or resuming from suspend; aci_status will 707 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 708 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 709 */ 710 cpun = psm_get_cpu_id(); 711 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 712 713 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 714 return (PSM_SUCCESS); 715 } 716 717 /* 718 * type == -1 indicates it is an internal request. Do not change 719 * resv_vector for these requests 720 */ 721 static int 722 apic_get_ipivect(int ipl, int type) 723 { 724 uchar_t vector; 725 int irq; 726 727 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 728 if ((vector = apic_allocate_vector(ipl, irq, 1))) { 729 apic_irq_table[irq]->airq_mps_intr_index = 730 RESERVE_INDEX; 731 apic_irq_table[irq]->airq_vector = vector; 732 if (type != -1) { 733 apic_resv_vector[ipl] = vector; 734 } 735 return (irq); 736 } 737 } 738 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 739 return (-1); /* shouldn't happen */ 740 } 741 742 static int 743 apic_getclkirq(int ipl) 744 { 745 int irq; 746 747 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 748 return (-1); 749 /* 750 * Note the vector in apic_clkvect for per clock handling. 751 */ 752 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 753 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 754 apic_clkvect)); 755 return (irq); 756 } 757 758 /* 759 * Try and disable all interrupts. We just assign interrupts to other 760 * processors based on policy. If any were bound by user request, we 761 * let them continue and return failure. We do not bother to check 762 * for cache affinity while rebinding. 763 */ 764 765 static int 766 apic_disable_intr(processorid_t cpun) 767 { 768 int bind_cpu = 0, i, hardbound = 0; 769 apic_irq_t *irq_ptr; 770 ulong_t iflag; 771 772 iflag = intr_clear(); 773 lock_set(&apic_ioapic_lock); 774 775 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 776 if (apic_reprogram_info[i].done == B_FALSE) { 777 if (apic_reprogram_info[i].bindcpu == cpun) { 778 /* 779 * CPU is busy -- it's the target of 780 * a pending reprogramming attempt 781 */ 782 lock_clear(&apic_ioapic_lock); 783 intr_restore(iflag); 784 return (PSM_FAILURE); 785 } 786 } 787 } 788 789 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 790 791 apic_cpus[cpun].aci_curipl = 0; 792 793 i = apic_min_device_irq; 794 for (; i <= apic_max_device_irq; i++) { 795 /* 796 * If there are bound interrupts on this cpu, then 797 * rebind them to other processors. 798 */ 799 if ((irq_ptr = apic_irq_table[i]) != NULL) { 800 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 801 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 802 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 803 804 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 805 hardbound = 1; 806 continue; 807 } 808 809 if (irq_ptr->airq_temp_cpu == cpun) { 810 do { 811 bind_cpu = 812 apic_find_cpu(APIC_CPU_INTR_ENABLE); 813 } while (apic_rebind_all(irq_ptr, bind_cpu)); 814 } 815 } 816 } 817 818 lock_clear(&apic_ioapic_lock); 819 intr_restore(iflag); 820 821 if (hardbound) { 822 cmn_err(CE_WARN, "Could not disable interrupts on %d" 823 "due to user bound interrupts", cpun); 824 return (PSM_FAILURE); 825 } 826 else 827 return (PSM_SUCCESS); 828 } 829 830 /* 831 * Bind interrupts to the CPU's local APIC. 832 * Interrupts should not be bound to a CPU's local APIC until the CPU 833 * is ready to receive interrupts. 834 */ 835 static void 836 apic_enable_intr(processorid_t cpun) 837 { 838 int i; 839 apic_irq_t *irq_ptr; 840 ulong_t iflag; 841 842 iflag = intr_clear(); 843 lock_set(&apic_ioapic_lock); 844 845 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 846 847 i = apic_min_device_irq; 848 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 849 if ((irq_ptr = apic_irq_table[i]) != NULL) { 850 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 851 (void) apic_rebind_all(irq_ptr, 852 irq_ptr->airq_cpu); 853 } 854 } 855 } 856 857 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 858 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 859 860 lock_clear(&apic_ioapic_lock); 861 intr_restore(iflag); 862 } 863 864 /* 865 * If this module needs a periodic handler for the interrupt distribution, it 866 * can be added here. The argument to the periodic handler is not currently 867 * used, but is reserved for future. 868 */ 869 static void 870 apic_post_cyclic_setup(void *arg) 871 { 872 _NOTE(ARGUNUSED(arg)) 873 874 cyc_handler_t cyh; 875 cyc_time_t cyt; 876 877 /* cpu_lock is held */ 878 /* set up a periodic handler for intr redistribution */ 879 880 /* 881 * In peridoc mode intr redistribution processing is done in 882 * apic_intr_enter during clk intr processing 883 */ 884 if (!apic_oneshot) 885 return; 886 887 /* 888 * Register a periodical handler for the redistribution processing. 889 * Though we would generally prefer to use the DDI interface for 890 * periodic handler invocation, ddi_periodic_add(9F), we are 891 * unfortunately already holding cpu_lock, which ddi_periodic_add will 892 * attempt to take for us. Thus, we add our own cyclic directly: 893 */ 894 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute; 895 cyh.cyh_arg = NULL; 896 cyh.cyh_level = CY_LOW_LEVEL; 897 898 cyt.cyt_when = 0; 899 cyt.cyt_interval = apic_redistribute_sample_interval; 900 901 apic_cyclic_id = cyclic_add(&cyh, &cyt); 902 } 903 904 static void 905 apic_redistribute_compute(void) 906 { 907 int i, j, max_busy; 908 909 if (apic_enable_dynamic_migration) { 910 if (++apic_nticks == apic_sample_factor_redistribution) { 911 /* 912 * Time to call apic_intr_redistribute(). 913 * reset apic_nticks. This will cause max_busy 914 * to be calculated below and if it is more than 915 * apic_int_busy, we will do the whole thing 916 */ 917 apic_nticks = 0; 918 } 919 max_busy = 0; 920 for (i = 0; i < apic_nproc; i++) { 921 if (!apic_cpu_in_range(i)) 922 continue; 923 924 /* 925 * Check if curipl is non zero & if ISR is in 926 * progress 927 */ 928 if (((j = apic_cpus[i].aci_curipl) != 0) && 929 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 930 931 int irq; 932 apic_cpus[i].aci_busy++; 933 irq = apic_cpus[i].aci_current[j]; 934 apic_irq_table[irq]->airq_busy++; 935 } 936 937 if (!apic_nticks && 938 (apic_cpus[i].aci_busy > max_busy)) 939 max_busy = apic_cpus[i].aci_busy; 940 } 941 if (!apic_nticks) { 942 if (max_busy > apic_int_busy_mark) { 943 /* 944 * We could make the following check be 945 * skipped > 1 in which case, we get a 946 * redistribution at half the busy mark (due to 947 * double interval). Need to be able to collect 948 * more empirical data to decide if that is a 949 * good strategy. Punt for now. 950 */ 951 if (apic_skipped_redistribute) { 952 apic_cleanup_busy(); 953 apic_skipped_redistribute = 0; 954 } else { 955 apic_intr_redistribute(); 956 } 957 } else 958 apic_skipped_redistribute++; 959 } 960 } 961 } 962 963 964 /* 965 * The following functions are in the platform specific file so that they 966 * can be different functions depending on whether we are running on 967 * bare metal or a hypervisor. 968 */ 969 970 /* 971 * Check to make sure there are enough irq slots 972 */ 973 int 974 apic_check_free_irqs(int count) 975 { 976 int i, avail; 977 978 avail = 0; 979 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 980 if ((apic_irq_table[i] == NULL) || 981 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 982 if (++avail >= count) 983 return (PSM_SUCCESS); 984 } 985 } 986 return (PSM_FAILURE); 987 } 988 989 /* 990 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 991 */ 992 int 993 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 994 int behavior) 995 { 996 int rcount, i; 997 uchar_t start, irqno; 998 uint32_t cpu; 999 major_t major; 1000 apic_irq_t *irqptr; 1001 1002 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1003 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1004 (void *)dip, inum, pri, count, behavior)); 1005 1006 if (count > 1) { 1007 if (behavior == DDI_INTR_ALLOC_STRICT && 1008 apic_multi_msi_enable == 0) 1009 return (0); 1010 if (apic_multi_msi_enable == 0) 1011 count = 1; 1012 } 1013 1014 if ((rcount = apic_navail_vector(dip, pri)) > count) 1015 rcount = count; 1016 else if (rcount == 0 || (rcount < count && 1017 behavior == DDI_INTR_ALLOC_STRICT)) 1018 return (0); 1019 1020 /* if not ISP2, then round it down */ 1021 if (!ISP2(rcount)) 1022 rcount = 1 << (highbit(rcount) - 1); 1023 1024 mutex_enter(&airq_mutex); 1025 1026 for (start = 0; rcount > 0; rcount >>= 1) { 1027 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1028 behavior == DDI_INTR_ALLOC_STRICT) 1029 break; 1030 } 1031 1032 if (start == 0) { 1033 /* no vector available */ 1034 mutex_exit(&airq_mutex); 1035 return (0); 1036 } 1037 1038 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1039 /* not enough free irq slots available */ 1040 mutex_exit(&airq_mutex); 1041 return (0); 1042 } 1043 1044 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1045 for (i = 0; i < rcount; i++) { 1046 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1047 (uchar_t)-1) { 1048 /* 1049 * shouldn't happen because of the 1050 * apic_check_free_irqs() check earlier 1051 */ 1052 mutex_exit(&airq_mutex); 1053 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1054 "apic_allocate_irq failed\n")); 1055 return (i); 1056 } 1057 apic_max_device_irq = max(irqno, apic_max_device_irq); 1058 apic_min_device_irq = min(irqno, apic_min_device_irq); 1059 irqptr = apic_irq_table[irqno]; 1060 #ifdef DEBUG 1061 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1062 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1063 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1064 #endif 1065 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1066 1067 irqptr->airq_vector = (uchar_t)(start + i); 1068 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1069 irqptr->airq_intin_no = (uchar_t)rcount; 1070 irqptr->airq_ipl = pri; 1071 irqptr->airq_vector = start + i; 1072 irqptr->airq_origirq = (uchar_t)(inum + i); 1073 irqptr->airq_share_id = 0; 1074 irqptr->airq_mps_intr_index = MSI_INDEX; 1075 irqptr->airq_dip = dip; 1076 irqptr->airq_major = major; 1077 if (i == 0) /* they all bound to the same cpu */ 1078 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1079 0xff, 0xff); 1080 else 1081 irqptr->airq_cpu = cpu; 1082 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1083 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1084 (void *)irqptr->airq_dip, irqptr->airq_vector, 1085 irqptr->airq_origirq, pri)); 1086 } 1087 mutex_exit(&airq_mutex); 1088 return (rcount); 1089 } 1090 1091 /* 1092 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1093 */ 1094 int 1095 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1096 int behavior) 1097 { 1098 int rcount, i; 1099 major_t major; 1100 1101 mutex_enter(&airq_mutex); 1102 1103 if ((rcount = apic_navail_vector(dip, pri)) > count) 1104 rcount = count; 1105 else if (rcount == 0 || (rcount < count && 1106 behavior == DDI_INTR_ALLOC_STRICT)) { 1107 rcount = 0; 1108 goto out; 1109 } 1110 1111 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1112 /* not enough free irq slots available */ 1113 rcount = 0; 1114 goto out; 1115 } 1116 1117 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1118 for (i = 0; i < rcount; i++) { 1119 uchar_t vector, irqno; 1120 apic_irq_t *irqptr; 1121 1122 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1123 (uchar_t)-1) { 1124 /* 1125 * shouldn't happen because of the 1126 * apic_check_free_irqs() check earlier 1127 */ 1128 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1129 "apic_allocate_irq failed\n")); 1130 rcount = i; 1131 goto out; 1132 } 1133 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1134 /* 1135 * shouldn't happen because of the 1136 * apic_navail_vector() call earlier 1137 */ 1138 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1139 "apic_allocate_vector failed\n")); 1140 rcount = i; 1141 goto out; 1142 } 1143 apic_max_device_irq = max(irqno, apic_max_device_irq); 1144 apic_min_device_irq = min(irqno, apic_min_device_irq); 1145 irqptr = apic_irq_table[irqno]; 1146 irqptr->airq_vector = (uchar_t)vector; 1147 irqptr->airq_ipl = pri; 1148 irqptr->airq_origirq = (uchar_t)(inum + i); 1149 irqptr->airq_share_id = 0; 1150 irqptr->airq_mps_intr_index = MSIX_INDEX; 1151 irqptr->airq_dip = dip; 1152 irqptr->airq_major = major; 1153 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1154 } 1155 out: 1156 mutex_exit(&airq_mutex); 1157 return (rcount); 1158 } 1159 1160 /* 1161 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1162 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1163 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1164 * requests and allocated only when pri is set. 1165 */ 1166 uchar_t 1167 apic_allocate_vector(int ipl, int irq, int pri) 1168 { 1169 int lowest, highest, i; 1170 1171 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1172 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1173 1174 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1175 lowest -= APIC_VECTOR_PER_IPL; 1176 1177 #ifdef DEBUG 1178 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1179 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1180 #endif /* DEBUG */ 1181 if (pri == 0) 1182 highest -= APIC_HI_PRI_VECTS; 1183 1184 for (i = lowest; i <= highest; i++) { 1185 if (APIC_CHECK_RESERVE_VECTORS(i)) 1186 continue; 1187 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1188 apic_vector_to_irq[i] = (uchar_t)irq; 1189 return (i); 1190 } 1191 } 1192 1193 return (0); 1194 } 1195 1196 /* Mark vector as not being used by any irq */ 1197 void 1198 apic_free_vector(uchar_t vector) 1199 { 1200 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1201 } 1202 1203 /* 1204 * Call rebind to do the actual programming. 1205 * Must be called with interrupts disabled and apic_ioapic_lock held 1206 * 'p' is polymorphic -- if this function is called to process a deferred 1207 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1208 * the irq pointer is retrieved. If not doing deferred reprogramming, 1209 * p is of the type 'apic_irq_t *'. 1210 * 1211 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1212 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1213 * taken offline after a cpu is selected, but before apic_rebind is called to 1214 * bind interrupts to it. 1215 */ 1216 int 1217 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1218 { 1219 apic_irq_t *irqptr; 1220 struct ioapic_reprogram_data *drep = NULL; 1221 int rv; 1222 1223 if (deferred) { 1224 drep = (struct ioapic_reprogram_data *)p; 1225 ASSERT(drep != NULL); 1226 irqptr = drep->irqp; 1227 } else 1228 irqptr = (apic_irq_t *)p; 1229 1230 ASSERT(irqptr != NULL); 1231 1232 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1233 if (rv) { 1234 /* 1235 * CPU is not up or interrupts are disabled. Fall back to 1236 * the first available CPU 1237 */ 1238 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1239 drep); 1240 } 1241 1242 return (rv); 1243 } 1244 1245 1246 uchar_t 1247 apic_modify_vector(uchar_t vector, int irq) 1248 { 1249 apic_vector_to_irq[vector] = (uchar_t)irq; 1250 return (vector); 1251 } 1252 1253 char * 1254 apic_get_apic_type(void) 1255 { 1256 return (apic_psm_info.p_mach_idstring); 1257 } 1258 1259 void 1260 apic_switch_ipi_callback(boolean_t enter) 1261 { 1262 ASSERT(enter == B_TRUE); 1263 } 1264 1265 int 1266 apic_detect_x2apic(void) 1267 { 1268 return (0); 1269 } 1270 1271 void 1272 apic_enable_x2apic(void) 1273 { 1274 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp"); 1275 } 1276 1277 void 1278 x2apic_update_psm(void) 1279 { 1280 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp"); 1281 }