1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2017 Joyent, Inc.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29
30 #ifndef _SYS_APIC_APIC_H
31 #define _SYS_APIC_APIC_H
32
33 #include <sys/psm_types.h>
34 #include <sys/avintr.h>
35 #include <sys/pci.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #include <sys/psm_common.h>
42
43 #define APIC_PCPLUSMP_NAME "pcplusmp"
44 #define APIC_APIX_NAME "apix"
45
46 #define APIC_IO_ADDR 0xfec00000
47 #define APIC_LOCAL_ADDR 0xfee00000
48 #define APIC_IO_MEMLEN 0xf
49 #define APIC_LOCAL_MEMLEN 0xfffff
50
51 /* Local Unit ID register */
52 #define APIC_LID_REG 0x8
53
54 /* I/o Unit Version Register */
55 #define APIC_VERS_REG 0xc
56
57 /* Task Priority register */
58 #define APIC_TASK_REG 0x20
59
60 /* EOI register */
61 #define APIC_EOI_REG 0x2c
62
63 /* Remote Read register */
64 #define APIC_REMOTE_READ 0x30
65
66 /* Logical Destination register */
67 #define APIC_DEST_REG 0x34
68
69 /* Destination Format register */
70 #define APIC_FORMAT_REG 0x38
71
72 /* Spurious Interrupt Vector register */
73 #define APIC_SPUR_INT_REG 0x3c
74
75 /* Error Status Register */
76 #define APIC_ERROR_STATUS 0xa0
77
78 /* Interrupt Command registers */
79 #define APIC_INT_CMD1 0xc0
80 #define APIC_INT_CMD2 0xc4
81
82 /* Local Interrupt Vector registers */
83 #define APIC_CMCI_VECT 0xbc
84 #define APIC_THERM_VECT 0xcc
85 #define APIC_PCINT_VECT 0xd0
86 #define APIC_INT_VECT0 0xd4
87 #define APIC_INT_VECT1 0xd8
88 #define APIC_ERR_VECT 0xdc
89
90 /* IPL for performance counter interrupts */
91 #define APIC_PCINT_IPL 0xe
92 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */
93
94 /* Initial Count register */
95 #define APIC_INIT_COUNT 0xe0
96
97 /* Current Count Register */
98 #define APIC_CURR_COUNT 0xe4
99 #define APIC_CURR_ADD 0x39 /* used for remote read command */
100 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT)
101
102 /* Divider Configuration Register */
103 #define APIC_DIVIDE_REG 0xf8
104
105 /* Various mode for local APIC. Modes are mutually exclusive */
106 typedef enum apic_mode {
107 APIC_IS_DISABLED = 0,
108 APIC_MODE_NOTSET,
109 LOCAL_APIC,
110 LOCAL_X2APIC
111 } apic_mode_t;
112
113 /* x2APIC SELF IPI Register */
114 #define X2APIC_SELF_IPI 0xFC
115
116 /* General x2APIC constants used at various places */
117 #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000
118 #define APIC_DIRECTED_EOI_BIT 0x1000000
119
120 /* x2APIC enable bit in REG_APIC_BASE_MSR */
121 #define X2APIC_ENABLE_BIT 10
122
123 /* IRR register */
124 #define APIC_IRR_REG 0x80
125
126 /* ISR register */
127 #define APIC_ISR_REG 0x40
128
129 #define APIC_IO_REG 0x0
130 #define APIC_IO_DATA 0x4
131 #define APIC_IO_EOI 0x10
132
133 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
134 #define APIC_ID_BIT_OFFSET 24
135 #define APIC_ICR_ID_BIT_OFFSET 24
136 #define APIC_LDR_ID_BIT_OFFSET 24
137
138 /*
139 * Choose between flat and clustered models by writing the following to the
140 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
141 * disable logical destination mode.
142 * Does not seem to be in the docs for local APICs on the processors.
143 */
144 #define APIC_FLAT_MODEL 0xFFFFFFFFUL
145 #define APIC_CLUSTER_MODEL 0x0FFFFFFF
146
147 /*
148 * The commands which follow are window selectors written to APIC_IO_REG
149 * before data can be read/written from/to APIC_IO_DATA
150 */
151
152 #define APIC_ID_CMD 0x0
153 #define APIC_VERS_CMD 0x1
154 #define APIC_RDT_CMD 0x10
155 #define APIC_RDT_CMD2 0x11
156
157 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */
158 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */
159
160 #define APIC_INT_SPURIOUS -1
161
162 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */
163 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */
164 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */
165 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */
166 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */
167
168 #define APIC_CT_VECT 0x4ac /* conf table vector */
169 #define APIC_CT_SIZE 1024 /* conf table size */
170
171 #define APIC_ID 'MPAT' /* conf table signature */
172
173 #define VENID_AMD 0x1022
174 #define DEVID_8131_IOAPIC 0x7451
175 #define DEVID_8132_IOAPIC 0x7459
176
177 #define IOAPICS_NODE_NAME "ioapics"
178 #define IOAPICS_CHILD_NAME "ioapic"
179 #define IOAPICS_DEV_TYPE "ioapic"
180 #define IOAPICS_PROP_VENID "vendor-id"
181 #define IOAPICS_PROP_DEVID "device-id"
182
183 #define IS_CLASS_IOAPIC(b, s, p) \
184 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \
185 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \
186 (p) == PCI_PERIPH_PIC_IF_IOX_APIC))
187
188 /*
189 * These macros are used in frequently called routines like
190 * apic_intr_enter().
191 */
192 #define X2APIC_WRITE(reg, v) \
193 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
194
195 #define LOCAL_APIC_WRITE_REG(reg, v) \
196 apicadr[reg] = v
197
198 /*
199 * MP floating pointer structure defined in Intel MP Spec 1.1
200 */
201 struct apic_mpfps_hdr {
202 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */
203 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */
204 uchar_t mpfps_length; /* in paragraph (16-bytes units) */
205 uchar_t mpfps_spec_rev; /* version number of MP spec */
206 uchar_t mpfps_checksum; /* checksum of complete structure */
207 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */
208 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */
209 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */
210 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */
211 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */
212 };
213
214 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */
215
216 #define APIC_MPS_OEM_ID_LEN 8
217 #define APIC_MPS_PROD_ID_LEN 12
218
219 struct apic_mp_cnf_hdr {
220 uint_t mpcnf_sig;
221
222 uint_t mpcnf_tbl_length: 16,
223 mpcnf_spec: 8,
224 mpcnf_cksum: 8;
225
226 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];
227
228 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN];
229
230 uint_t mpcnf_oem_ptr;
231
232 uint_t mpcnf_oem_tbl_size: 16,
233 mpcnf_entry_cnt: 16;
234
235 uint_t mpcnf_local_apic;
236
237 uint_t mpcnf_resv;
238 };
239
240 struct apic_procent {
241 uint_t proc_entry: 8,
242 proc_apicid: 8,
243 proc_version: 8,
244 proc_cpuflags: 8;
245
246 uint_t proc_stepping: 4,
247 proc_model: 4,
248 proc_family: 4,
249 proc_type: 2, /* undocumented feature */
250 proc_resv1: 18;
251
252 uint_t proc_feature;
253
254 uint_t proc_resv2;
255
256 uint_t proc_resv3;
257 };
258
259 /*
260 * proc_cpuflags definitions
261 */
262 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */
263 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */
264
265
266 struct apic_bus {
267 uchar_t bus_entry;
268 uchar_t bus_id;
269 ushort_t bus_str1;
270 uint_t bus_str2;
271 };
272
273 struct apic_io_entry {
274 uint_t io_entry: 8,
275 io_apicid: 8,
276 io_version: 8,
277 io_flags: 8;
278
279 uint_t io_apic_addr;
280 };
281
282 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */
283
284 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */
285
286 struct apic_io_intr {
287 uint_t intr_entry: 8,
288 intr_type: 8,
289 intr_po: 2,
290 intr_el: 2,
291 intr_resv: 12;
292
293 uint_t intr_busid: 8,
294 intr_irq: 8,
295 intr_destid: 8,
296 intr_destintin: 8;
297 };
298
299 /*
300 * intr_type definitions
301 */
302 #define IO_INTR_INT 0x00
303 #define IO_INTR_NMI 0x01
304 #define IO_INTR_SMI 0x02
305 #define IO_INTR_EXTINT 0x03
306
307 /*
308 * destination APIC ID
309 */
310 #define INTR_ALL_APIC 0xff
311
312
313 /* local vector table */
314 #define AV_MASK 0x10000
315
316 /* interrupt command register 32-63 */
317 #define AV_TOALL 0x7fffffff
318 #define AV_HIGH_ORDER 0x40000000
319 #define AV_IM_OFF 0x40000000
320
321 /* interrupt command register 0-31 */
322 #define AV_DELIV_MODE 0x700
323
324 #define AV_FIXED 0x000
325 #define AV_LOPRI 0x100
326 #define AV_SMI 0x200
327 #define AV_REMOTE 0x300
328 #define AV_NMI 0x400
329 #define AV_RESET 0x500
330 #define AV_STARTUP 0x600
331 #define AV_EXTINT 0x700
332
333 #define AV_PDEST 0x000
334 #define AV_LDEST 0x800
335
336 /* IO & Local APIC Bit Definitions */
337 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF))
338 #define AV_PENDING 0x1000
339 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */
340 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */
341 #define AV_LEVEL 0x8000
342 #define AV_DEASSERT AV_LEVEL
343 #define AV_ASSERT 0xc000
344
345 #define AV_READ_PENDING 0x10000
346 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */
347
348 #define AV_SH_SELF 0x40000 /* Short hand for self */
349 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */
350 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */
351 /* spurious interrupt vector register */
352 #define AV_UNIT_ENABLE 0x100
353
354 #define APIC_MAXVAL 0xffffffffUL
355 #define APIC_TIME_MIN 0x5000
356 #define APIC_TIME_COUNT 0x4000
357
358 /*
359 * Range of the low byte value in apic_tick before starting calibration
360 */
361 #define APIC_LB_MIN 0x60
362 #define APIC_LB_MAX 0xe0
363
364 #define APIC_MAX_VECTOR 255
365 #define APIC_RESV_VECT 0x00
366 #define APIC_RESV_IRQ 0xfe
367 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */
368 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT)
369 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */
370 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT)
371 #define APIC_VECTOR_MASK 0x0f
372 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */
373 #define APIC_IPL_MASK 0xf0
374 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */
375 #define APIC_FIRST_FREE_IRQ 0x10
376 #define APIC_MAX_ISA_IRQ 15
377 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */
378 #define APIC_IDLE_IPL 0x00
379
380 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */
381
382 /* spurious interrupt vector */
383 #define APIC_SPUR_INTR 0xFF
384
385 /* special or reserve vectors */
386 #define APIC_CHECK_RESERVE_VECTORS(v) \
387 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
388 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET))
389
390 /* cmos shutdown code for BIOS */
391 #define BIOS_SHUTDOWN 0x0a
392
393 /* define the entry types for BIOS information tables as defined in PC+MP */
394 #define APIC_CPU_ENTRY 0
395 #define APIC_BUS_ENTRY 1
396 #define APIC_IO_ENTRY 2
397 #define APIC_IO_INTR_ENTRY 3
398 #define APIC_LOCAL_INTR_ENTRY 4
399 #define APIC_MPTBL_ADDR (639 * 1024)
400 /*
401 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
402 * of system base memory or in ROM between 0xF0000 and 0xFFFFF
403 */
404 #define MPFPS_RAM_WIN_LEN 1024
405 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000
406 #define MPFPS_ROM_WIN_LEN 0x10000
407
408 #define EISA_LEVEL_CNTL 0x4D0
409
410 /* definitions for apic_irq_table */
411 #define FREE_INDEX (short)-1 /* empty slot */
412 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */
413 #define ACPI_INDEX (short)-3 /* ACPI */
414 #define MSI_INDEX (short)-4 /* MSI */
415 #define MSIX_INDEX (short)-5 /* MSI-X */
416 #define DEFAULT_INDEX (short)0x7FFF
417 /* biggest positive no. to avoid conflict with actual index */
418
419 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \
420 ((index) == MSI_INDEX || (index) == MSIX_INDEX)
421
422 /*
423 * definitions for MSI Address
424 */
425 #define MSI_ADDR_HDR APIC_LOCAL_ADDR
426 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */
427 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */
428 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */
429 #define MSI_ADDR_RH_SHIFT 3
430 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */
431 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */
432 #define MSI_ADDR_DM_SHIFT 2
433
434 /*
435 * TM is either edge or level.
436 */
437 #define TRIGGER_MODE_EDGE 0x0 /* edge sensitive */
438 #define TRIGGER_MODE_LEVEL 0x1 /* level sensitive */
439
440 /*
441 * definitions for MSI Data
442 */
443 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */
444 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */
445 #define MSI_DATA_DELIVERY_SMI 0x2
446 #define MSI_DATA_DELIVERY_NMI 0x4
447 #define MSI_DATA_DELIVERY_INIT 0x5
448 #define MSI_DATA_DELIVERY_EXTINT 0x7
449 #define MSI_DATA_DELIVERY_SHIFT 8
450 #define MSI_DATA_TM_EDGE TRIGGER_MODE_EDGE
451 #define MSI_DATA_TM_LEVEL TRIGGER_MODE_LEVEL
452 #define MSI_DATA_TM_SHIFT 15
453 #define MSI_DATA_LEVEL_DEASSERT 0x0
454 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */
455 #define MSI_DATA_LEVEL_SHIFT 14
456
457 /*
458 * use to define each irq setup by the apic
459 */
460 typedef struct apic_irq {
461 short airq_mps_intr_index; /* index into mps interrupt entries */
462 /* table */
463 uchar_t airq_intin_no;
464 uchar_t airq_ioapicindex;
465 dev_info_t *airq_dip; /* device corresponding to this interrupt */
466 /*
467 * IRQ could be shared (in H/W) in which case dip & major will be
468 * for the one that was last added at this level. We cannot keep a
469 * linked list as delspl does not tell us which device has just
470 * been unloaded. For most servers where we are worried about
471 * performance, interrupt should not be shared & should not be
472 * a problem. This does not cause any correctness issue - dip is
473 * used only as an optimisation to avoid going thru all the tables
474 * in translate IRQ (which is always called twice due to brokenness
475 * in the way IPLs are determined for devices). major is used only
476 * to bind interrupts corresponding to the same device on the same
477 * CPU. Not finding major will just cause it to be potentially bound
478 * to another CPU.
479 */
480 major_t airq_major; /* major number corresponding to the device */
481 ushort_t airq_rdt_entry; /* level, polarity & trig mode */
482 uint32_t airq_cpu; /* target CPU, non-reserved IRQ only */
483 uint32_t airq_temp_cpu; /* non-reserved IRQ only, for disable_intr */
484 uchar_t airq_vector; /* Vector chosen for this irq */
485 uchar_t airq_share; /* number of interrupts at this irq */
486 uchar_t airq_share_id; /* id to identify source from irqno */
487 uchar_t airq_ipl; /* The ipl at which this is handled */
488 iflag_t airq_iflag; /* interrupt flag */
489 uchar_t airq_origirq; /* original irq passed in */
490 uint_t airq_busy; /* How frequently did clock find */
491 /* us in this */
492 struct apic_irq *airq_next; /* chain of intpts sharing a vector */
493 void *airq_intrmap_private; /* intr remap private data */
494 } apic_irq_t;
495
496 #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */
497 #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */
498 #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */
499
500 /* Macros to help deal with shared interrupts */
501 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8))
502 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */
503
504 /*
505 * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we
506 * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also
507 * don't want the compiler to optimize apic_cpus_info.
508 */
509 #define APIC_PADSZ 15
510
511 #pragma pack(1)
512 typedef struct apic_cpus_info {
513 uint32_t aci_local_id;
514 uchar_t aci_local_ver;
515 uchar_t aci_status;
516 uchar_t aci_redistribute; /* Selected for redistribution */
517 uint_t aci_busy; /* Number of ticks we were in ISR */
518 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */
519 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */
520 uchar_t aci_curipl; /* IPL of current ISR */
521 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */
522 uint32_t aci_bound; /* # of user requested binds ? */
523 uint32_t aci_temp_bound; /* # of non user IRQ binds */
524 uint32_t aci_processor_id; /* Only used in ACPI mode. */
525 uchar_t aci_idle; /* The CPU is idle */
526 /*
527 * Fill to make sure each struct is in separate 64-byte cache line.
528 */
529 uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */
530 } apic_cpus_info_t;
531 #pragma pack()
532
533 #define APIC_CPU_ONLINE 0x1
534 #define APIC_CPU_INTR_ENABLE 0x2
535 #define APIC_CPU_FREE 0x4 /* APIC CPU slot is free */
536 #define APIC_CPU_DIRTY 0x8 /* Slot was once used */
537 #define APIC_CPU_SUSPEND 0x10
538
539 /*
540 * APIC ops to support various flavors of APIC like APIC and x2APIC.
541 */
542 typedef struct apic_regs_ops {
543 uint64_t (*apic_read)(uint32_t);
544 void (*apic_write)(uint32_t, uint64_t);
545 int (*apic_get_pri)(void);
546 void (*apic_write_task_reg)(uint64_t);
547 void (*apic_write_int_cmd)(uint32_t, uint32_t);
548 void (*apic_send_eoi)(uint32_t);
549 } apic_reg_ops_t;
550
551 /*
552 * interrupt structure for ioapic and msi
553 */
554 typedef struct ioapic_rdt {
555 uint32_t ir_lo;
556 uint32_t ir_hi;
557 } ioapic_rdt_t;
558
559 typedef struct msi_regs {
560 uint32_t mr_data;
561 uint64_t mr_addr;
562 }msi_regs_t;
563
564 /*
565 * APIC ops to support intel interrupt remapping
566 */
567 typedef struct apic_intrmap_ops {
568 int (*apic_intrmap_init)(int);
569 void (*apic_intrmap_enable)(int);
570 void (*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t,
571 int, uchar_t);
572 void (*apic_intrmap_map_entry)(void *, void *, uint16_t, int);
573 void (*apic_intrmap_free_entry)(void **);
574 void (*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *);
575 void (*apic_intrmap_record_msi)(void *, msi_regs_t *);
576 } apic_intrmap_ops_t;
577
578 /*
579 * Various poweroff methods and ports & bits for them
580 */
581 #define APIC_POWEROFF_NONE 0
582 #define APIC_POWEROFF_VIA_RTC 1
583 #define APIC_POWEROFF_VIA_ASPEN_BMC 2
584 #define APIC_POWEROFF_VIA_SITKA_BMC 3
585
586 /* For RTC */
587 #define RTC_REGA 0x0a
588 #define PFR_REG 0x4a /* extended control register */
589 #define PAB_CBIT 0x08
590 #define WF_FLAG 0x02
591 #define KS_FLAG 0x01
592 #define EXT_BANK 0x10
593
594 /* For Aspen/Drake BMC */
595
596 #define CC_SMS_GET_STATUS 0x40
597 #define CC_SMS_WR_START 0x41
598 #define CC_SMS_WR_NEXT 0x42
599 #define CC_SMS_WR_END 0x43
600
601 #define MISMIC_DATA_REGISTER 0x0ca9
602 #define MISMIC_CNTL_REGISTER 0x0caa
603 #define MISMIC_FLAG_REGISTER 0x0cab
604
605 #define MISMIC_BUSY_MASK 0x01
606
607 /* For Sitka/Cabrillo BMC */
608
609 #define SMS_GET_STATUS 0x60
610 #define SMS_WRITE_START 0x61
611 #define SMS_WRITE_END 0x62
612
613 #define SMS_DATA_REGISTER 0x0ca2
614 #define SMS_STATUS_REGISTER 0x0ca3
615 #define SMS_COMMAND_REGISTER 0x0ca3
616
617 #define SMS_IBF_MASK 0x02
618 #define SMS_STATE_MASK 0xc0
619
620 #define SMS_IDLE_STATE 0x00
621 #define SMS_READ_STATE 0x40
622 #define SMS_WRITE_STATE 0x80
623 #define SMS_ERROR_STATE 0xc0
624
625 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
626 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
627 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value);
628
629 /* Macros for reading/writing the IOAPIC RDT entries */
630 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \
631 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)))
632
633 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \
634 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)))
635
636 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \
637 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value)
638
639 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \
640 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value)
641
642 /* Used by PSM_INTR_OP_GET_INTR to return device information. */
643 typedef struct {
644 uint16_t avgi_req_flags; /* request flags - to kernel */
645 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */
646 uint8_t avgi_vector; /* vector */
647 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */
648 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */
649 /* Contains num_devs elements. */
650 } apic_get_intr_t;
651
652 /* Used by PSM_INTR_OP_GET_TYPE to return platform information. */
653 typedef struct {
654 char *avgi_type; /* platform type - from kernel */
655 uint32_t avgi_num_intr; /* max intr number - from kernel */
656 uint32_t avgi_num_cpu; /* max cpu number - from kernel */
657 } apic_get_type_t;
658
659 /* Masks for avgi_req_flags. */
660 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */
661 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */
662 #define PSMGI_REQ_VECTOR 0x4
663 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */
664 #define PSMGI_REQ_ALL 0xf /* Request everything */
665
666 /* Other flags */
667 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */
668 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */
669 #define PSMGI_INTRBY_DEFAULT 0x4000 /* PSM specific default value */
670 #define PSMGI_INTRBY_FLAGS 0xc000 /* Mask for this flag */
671
672 extern int apic_verbose;
673
674 /* Flag definitions for apic_verbose */
675 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001
676 #define APIC_VERBOSE_IRQ_FLAG 0x00000002
677 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004
678 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008
679 #define APIC_VERBOSE_INIT 0x00000010
680 #define APIC_VERBOSE_REBIND 0x00000020
681 #define APIC_VERBOSE_ALLOC 0x00000040
682 #define APIC_VERBOSE_IPI 0x00000080
683 #define APIC_VERBOSE_INTR 0x00000100
684
685 /* required test to wait until APIC command is sent on the bus */
686 #define APIC_AV_PENDING_SET() \
687 while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \
688 apic_ret();
689
690 #ifdef DEBUG
691
692 #define DENT 0x0001
693 extern int apic_debug;
694 /*
695 * set apic_restrict_vector to the # of vectors we want to allow per range
696 * useful in testing shared interrupt logic by setting it to 2 or 3
697 */
698 extern int apic_restrict_vector;
699
700 #define APIC_DEBUG_MSGBUFSIZE 2048
701 extern int apic_debug_msgbuf[];
702 extern int apic_debug_msgbufindex;
703
704 /*
705 * Put "int" info into debug buffer. No MP consistency, but light weight.
706 * Good enough for most debugging.
707 */
708 #define APIC_DEBUG_BUF_PUT(x) \
709 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
710 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \
711 apic_debug_msgbufindex = 0;
712
713 #define APIC_VERBOSE(flag, fmt) \
714 if (apic_verbose & APIC_VERBOSE_##flag) \
715 cmn_err fmt;
716
717 #define APIC_VERBOSE_POWEROFF(fmt) \
718 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
719 prom_printf fmt;
720
721 #else /* DEBUG */
722
723 #define APIC_VERBOSE(flag, fmt)
724 #define APIC_VERBOSE_POWEROFF(fmt)
725
726 #endif /* DEBUG */
727
728 #define APIC_VERBOSE_IOAPIC(fmt) APIC_VERBOSE(IOAPIC_FLAG, fmt)
729 #define APIC_VERBOSE_IRQ(fmt) APIC_VERBOSE(IRQ_FLAG, fmt)
730
731 extern int apic_error;
732 /* values which apic_error can take. Not catastrophic, but may help debug */
733 #define APIC_ERR_BOOT_EOI 0x1
734 #define APIC_ERR_GET_IPIVECT_FAIL 0x2
735 #define APIC_ERR_INVALID_INDEX 0x4
736 #define APIC_ERR_MARK_VECTOR_FAIL 0x8
737 #define APIC_ERR_APIC_ERROR 0x40000000
738 #define APIC_ERR_NMI 0x80000000
739
740 /*
741 * ACPI definitions
742 */
743 /* _PIC method arguments */
744 #define ACPI_PIC_MODE 0
745 #define ACPI_APIC_MODE 1
746
747 /* APIC error flags we care about */
748 #define APIC_SEND_CS_ERROR 0x01
749 #define APIC_RECV_CS_ERROR 0x02
750 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR)
751
752 /* Maximum number of times to retry reprogramming at apic_intr_exit time */
753 #define APIC_REPROGRAM_MAX_TRIES 10000
754
755 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */
756 #define IOAPIC_MASK 1
757 #define IOAPIC_NOMASK 0
758
759 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0
760 #define INTR_ROUND_ROBIN 1
761 #define INTR_LOWEST_PRIORITY 2
762
763 struct ioapic_reprogram_data {
764 boolean_t done;
765 apic_irq_t *irqp;
766 /* The CPU to which the int will be bound */
767 int bindcpu;
768 /* # times the reprogram timeout was called */
769 unsigned tries;
770 };
771
772 /* The irq # is implicit in the array index: */
773 extern struct ioapic_reprogram_data apic_reprogram_info[];
774
775 extern void apic_intr_exit(int ipl, int irq);
776 extern void x2apic_intr_exit(int ipl, int irq);
777 extern int apic_probe_common();
778 extern void apic_init_common();
779 extern void ioapic_init_intr();
780 extern void ioapic_disable_redirection();
781 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
782 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
783 extern void apic_cleanup_busy();
784 extern void apic_intr_redistribute();
785 extern uchar_t apic_xlate_vector(uchar_t vector);
786 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri);
787 extern void apic_free_vector(uchar_t vector);
788 extern int apic_allocate_irq(int irq);
789 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid,
790 uchar_t intin);
791 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu,
792 struct ioapic_reprogram_data *drep);
793 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu);
794 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type);
795 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
796 psm_intr_op_t intr_op, int *result);
797 extern int apic_state(psm_state_request_t *);
798 extern boolean_t apic_cpu_in_range(int cpu);
799 extern int apic_check_msi_support();
800 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec,
801 int type);
802 extern int apic_navail_vector(dev_info_t *dip, int pri);
803 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count,
804 int pri, int behavior);
805 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count,
806 int pri, int behavior);
807 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri,
808 int type);
809 extern int apic_get_vector_intr_info(int vecirq,
810 apic_get_intr_t *intr_params_p);
811 extern uchar_t apic_find_multi_vectors(int pri, int count);
812 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred);
813 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags);
814 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags);
815 extern void mapout_apic(caddr_t addr, size_t len);
816 extern void mapout_ioapic(caddr_t addr, size_t len);
817 extern uchar_t apic_modify_vector(uchar_t vector, int irq);
818 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum);
819 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type);
820 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum);
821 extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum,
822 int vector, int count, int target_apic_id);
823 extern char *apic_get_apic_type();
824 extern uint16_t apic_get_apic_version();
825 extern void x2apic_send_ipi();
826 extern void apic_ret();
827 extern int apic_detect_x2apic();
828 extern void apic_enable_x2apic();
829 extern int apic_local_mode();
830 extern void apic_change_eoi();
831 extern void apic_send_EOI(uint32_t);
832 extern void apic_send_directed_EOI(uint32_t);
833 extern uint_t apic_calibrate(volatile uint32_t *, uint16_t *);
834
835 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */
836 extern int apic_forceload;
837 extern apic_cpus_info_t *apic_cpus;
838 #ifdef _MACHDEP
839 extern cpuset_t apic_cpumask;
840 #endif
841 extern uint_t apic_picinit_called;
842 extern uchar_t apic_ipltopri[MAXIPL+1];
843 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1];
844 extern int apic_max_device_irq;
845 extern int apic_min_device_irq;
846 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
847 extern volatile uint32_t *apicioadr[MAX_IO_APIC];
848 extern uchar_t apic_io_id[MAX_IO_APIC];
849 extern lock_t apic_ioapic_lock;
850 extern uint32_t apic_physaddr[MAX_IO_APIC];
851 extern kmutex_t airq_mutex;
852 extern int apic_first_avail_irq;
853 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL];
854 extern int apic_imcrp;
855 extern int apic_revector_pending;
856 extern char apic_level_intr[APIC_MAX_VECTOR+1];
857 extern uchar_t apic_resv_vector[MAXIPL+1];
858 extern int apic_sample_factor_redistribution;
859 extern int apic_int_busy_mark;
860 extern int apic_int_free_mark;
861 extern int apic_diff_for_redistribution;
862 extern int apic_poweroff_method;
863 extern int apic_enable_acpi;
864 extern int apic_nproc;
865 extern int apic_max_nproc;
866 extern int apic_next_bind_cpu;
867 extern int apic_redistribute_sample_interval;
868 extern int apic_multi_msi_enable;
869 extern int apic_sci_vect;
870 extern int apic_hpet_vect;
871 extern uchar_t apic_ipls[];
872 extern apic_reg_ops_t *apic_reg_ops;
873 extern apic_reg_ops_t local_apic_regs_ops;
874 extern apic_mode_t apic_mode;
875 extern void x2apic_update_psm();
876 extern void apic_change_ops();
877 extern void apic_common_send_ipi(int, int);
878 extern void apic_set_directed_EOI_handler();
879 extern int apic_directed_EOI_supported();
880
881 extern apic_intrmap_ops_t *apic_vt_ops;
882
883 #ifdef __cplusplus
884 }
885 #endif
886
887 #endif /* _SYS_APIC_APIC_H */