1589 }
1590
1591 return (PSM_SUCCESS);
1592 }
1593
1594 static char *
1595 apix_get_apic_type(void)
1596 {
1597 return (apix_psm_info.p_mach_idstring);
1598 }
1599
1600 apix_vector_t *
1601 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1602 {
1603 apix_vector_t *newp = NULL;
1604 dev_info_t *dip;
1605 int inum, cap_ptr;
1606 ddi_acc_handle_t handle;
1607 ddi_intr_msix_t *msix_p = NULL;
1608 ushort_t msix_ctrl;
1609 uintptr_t off;
1610 uint32_t mask;
1611
1612 ASSERT(LOCK_HELD(&apix_lock));
1613 *result = ENXIO;
1614
1615 /* Fail if this is an MSI intr and is part of a group. */
1616 if (vecp->v_type == APIX_TYPE_MSI) {
1617 if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1618 return (NULL);
1619 else
1620 return (apix_grp_set_cpu(vecp, new_cpu, result));
1621 }
1622
1623 /*
1624 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1625 */
1626 if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1627 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1628 return (NULL);
1629 inum = vecp->v_devp->dv_inum;
1630
1648 *result = 0;
1649 if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1650 *result = EIO;
1651
1652 /* Restore mask bit */
1653 if (msix_p != NULL)
1654 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1655
1656 return (newp);
1657 }
1658
1659 /*
1660 * Set cpu for MSIs
1661 */
1662 apix_vector_t *
1663 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1664 {
1665 apix_vector_t *newp, *vp;
1666 uint32_t orig_cpu = vecp->v_cpuid;
1667 int orig_vect = vecp->v_vector;
1668 int i, num_vectors, cap_ptr, msi_mask_off;
1669 uint32_t msi_pvm;
1670 ushort_t msi_ctrl;
1671 ddi_acc_handle_t handle;
1672 dev_info_t *dip;
1673
1674 APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1675 " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1676
1677 ASSERT(LOCK_HELD(&apix_lock));
1678
1679 *result = ENXIO;
1680
1681 if (vecp->v_type != APIX_TYPE_MSI) {
1682 DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1683 return (NULL);
1684 }
1685
1686 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1687 return (NULL);
1688
1689 num_vectors = i_ddi_intr_get_current_nintrs(dip);
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1589 }
1590
1591 return (PSM_SUCCESS);
1592 }
1593
1594 static char *
1595 apix_get_apic_type(void)
1596 {
1597 return (apix_psm_info.p_mach_idstring);
1598 }
1599
1600 apix_vector_t *
1601 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1602 {
1603 apix_vector_t *newp = NULL;
1604 dev_info_t *dip;
1605 int inum, cap_ptr;
1606 ddi_acc_handle_t handle;
1607 ddi_intr_msix_t *msix_p = NULL;
1608 ushort_t msix_ctrl;
1609 uintptr_t off = 0;
1610 uint32_t mask = 0;
1611
1612 ASSERT(LOCK_HELD(&apix_lock));
1613 *result = ENXIO;
1614
1615 /* Fail if this is an MSI intr and is part of a group. */
1616 if (vecp->v_type == APIX_TYPE_MSI) {
1617 if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1618 return (NULL);
1619 else
1620 return (apix_grp_set_cpu(vecp, new_cpu, result));
1621 }
1622
1623 /*
1624 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1625 */
1626 if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1627 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1628 return (NULL);
1629 inum = vecp->v_devp->dv_inum;
1630
1648 *result = 0;
1649 if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1650 *result = EIO;
1651
1652 /* Restore mask bit */
1653 if (msix_p != NULL)
1654 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1655
1656 return (newp);
1657 }
1658
1659 /*
1660 * Set cpu for MSIs
1661 */
1662 apix_vector_t *
1663 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1664 {
1665 apix_vector_t *newp, *vp;
1666 uint32_t orig_cpu = vecp->v_cpuid;
1667 int orig_vect = vecp->v_vector;
1668 int i, num_vectors, cap_ptr, msi_mask_off = 0;
1669 uint32_t msi_pvm = 0;
1670 ushort_t msi_ctrl;
1671 ddi_acc_handle_t handle;
1672 dev_info_t *dip;
1673
1674 APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1675 " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1676
1677 ASSERT(LOCK_HELD(&apix_lock));
1678
1679 *result = ENXIO;
1680
1681 if (vecp->v_type != APIX_TYPE_MSI) {
1682 DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1683 return (NULL);
1684 }
1685
1686 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1687 return (NULL);
1688
1689 num_vectors = i_ddi_intr_get_current_nintrs(dip);
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