1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 */
26 /*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30
31 /*
32 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
33 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
34 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
35 * PSMI 1.5 extensions are supported in Solaris Nevada.
36 * PSMI 1.6 extensions are supported in Solaris Nevada.
37 * PSMI 1.7 extensions are supported in Solaris Nevada.
38 */
39 #define PSMI_1_7
40
41 #include <sys/processor.h>
42 #include <sys/time.h>
43 #include <sys/psm.h>
44 #include <sys/smp_impldefs.h>
45 #include <sys/cram.h>
46 #include <sys/acpi/acpi.h>
47 #include <sys/acpica.h>
48 #include <sys/psm_common.h>
49 #include <sys/apic.h>
50 #include <sys/apic_timer.h>
51 #include <sys/pit.h>
52 #include <sys/ddi.h>
53 #include <sys/sunddi.h>
54 #include <sys/ddi_impldefs.h>
55 #include <sys/pci.h>
56 #include <sys/promif.h>
57 #include <sys/x86_archext.h>
58 #include <sys/cpc_impl.h>
59 #include <sys/uadmin.h>
60 #include <sys/panic.h>
61 #include <sys/debug.h>
62 #include <sys/archsystm.h>
63 #include <sys/trap.h>
64 #include <sys/machsystm.h>
65 #include <sys/cpuvar.h>
66 #include <sys/rm_platter.h>
67 #include <sys/privregs.h>
68 #include <sys/cyclic.h>
69 #include <sys/note.h>
70 #include <sys/pci_intr_lib.h>
71 #include <sys/sunndi.h>
72 #if !defined(__xpv)
73 #include <sys/hpet.h>
74 #include <sys/clock.h>
75 #endif
76
77 /*
78 * Local Function Prototypes
79 */
80 static int apic_handle_defconf();
81 static int apic_parse_mpct(caddr_t mpct, int bypass);
82 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
83 static int apic_checksum(caddr_t bptr, int len);
84 static int apic_find_bus_type(char *bus);
85 static int apic_find_bus(int busid);
86 static struct apic_io_intr *apic_find_io_intr(int irqno);
87 static int apic_find_free_irq(int start, int end);
88 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
89 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
90 static void apic_free_apic_cpus(void);
91 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
92 static int apic_acpi_enter_apicmode(void);
93
94 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
95 int child_ipin, struct apic_io_intr **intrp);
96 int apic_find_bus_id(int bustype);
97 int apic_find_intin(uchar_t ioapic, uchar_t intin);
98 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
99
100 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
101
102 /* ACPI SCI interrupt configuration; -1 if SCI not used */
103 int apic_sci_vect = -1;
104 iflag_t apic_sci_flags;
105
106 #if !defined(__xpv)
107 /* ACPI HPET interrupt configuration; -1 if HPET not used */
108 int apic_hpet_vect = -1;
109 iflag_t apic_hpet_flags;
110 #endif
111
112 /*
113 * psm name pointer
114 */
115 char *psm_name;
116
117 /* ACPI support routines */
118 static int acpi_probe(char *);
119 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
120 int *pci_irqp, iflag_t *intr_flagp);
121
122 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
123 int ipin, int *pci_irqp, iflag_t *intr_flagp);
124 uchar_t acpi_find_ioapic(int irq);
125 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
126
127 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
128 int apic_max_reps_clear_pending = 1000;
129
130 int apic_intr_policy = INTR_ROUND_ROBIN;
131
132 int apic_next_bind_cpu = 1; /* For round robin assignment */
133 /* start with cpu 1 */
134
135 /*
136 * If enabled, the distribution works as follows:
137 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
138 * and the irq corresponding to the ipl is also set in the aci_current array.
139 * interrupt exit and setspl (due to soft interrupts) will cause the current
140 * ipl to be be changed. This is cache friendly as these frequently used
141 * paths write into a per cpu structure.
142 *
143 * Sampling is done by checking the structures for all CPUs and incrementing
144 * the busy field of the irq (if any) executing on each CPU and the busy field
145 * of the corresponding CPU.
146 * In periodic mode this is done on every clock interrupt.
147 * In one-shot mode, this is done thru a cyclic with an interval of
148 * apic_redistribute_sample_interval (default 10 milli sec).
149 *
150 * Every apic_sample_factor_redistribution times we sample, we do computations
151 * to decide which interrupt needs to be migrated (see comments
152 * before apic_intr_redistribute().
153 */
154
155 /*
156 * Following 3 variables start as % and can be patched or set using an
157 * API to be defined in future. They will be scaled to
158 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
159 * mode), or 101 in one-shot mode to stagger it away from one sec processing
160 */
161
162 int apic_int_busy_mark = 60;
163 int apic_int_free_mark = 20;
164 int apic_diff_for_redistribution = 10;
165
166 /* sampling interval for interrupt redistribution for dynamic migration */
167 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
168
169 /*
170 * number of times we sample before deciding to redistribute interrupts
171 * for dynamic migration
172 */
173 int apic_sample_factor_redistribution = 101;
174
175 int apic_redist_cpu_skip = 0;
176 int apic_num_imbalance = 0;
177 int apic_num_rebind = 0;
178
179 /*
180 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
181 * allocation of CPU ids is disabled.
182 */
183 int apic_max_nproc = -1;
184 int apic_nproc = 0;
185 size_t apic_cpus_size = 0;
186 int apic_defconf = 0;
187 int apic_irq_translate = 0;
188 int apic_spec_rev = 0;
189 int apic_imcrp = 0;
190
191 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
192 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
193
194 /*
195 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
196 * will be assigned (via _SRS). If it is not set, use the current
197 * irq setting (via _CRS), but only if that irq is in the set of possible
198 * irqs (returned by _PRS) for the device.
199 */
200 int apic_unconditional_srs = 1;
201
202 /*
203 * For interrupt link devices, if apic_prefer_crs is set when we are
204 * assigning an IRQ resource to a device, prefer the current IRQ setting
205 * over other possible irq settings under same conditions.
206 */
207
208 int apic_prefer_crs = 1;
209
210 uchar_t apic_io_id[MAX_IO_APIC];
211 volatile uint32_t *apicioadr[MAX_IO_APIC];
212 uchar_t apic_io_ver[MAX_IO_APIC];
213 uchar_t apic_io_vectbase[MAX_IO_APIC];
214 uchar_t apic_io_vectend[MAX_IO_APIC];
215 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
216 uint32_t apic_physaddr[MAX_IO_APIC];
217
218 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
219
220 /*
221 * First available slot to be used as IRQ index into the apic_irq_table
222 * for those interrupts (like MSI/X) that don't have a physical IRQ.
223 */
224 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
225
226 /*
227 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
228 * and bound elements of cpus_info and the temp_cpu element of irq_struct
229 */
230 lock_t apic_ioapic_lock;
231
232 int apic_io_max = 0; /* no. of i/o apics enabled */
233
234 struct apic_io_intr *apic_io_intrp = NULL;
235 static struct apic_bus *apic_busp;
236
237 uchar_t apic_resv_vector[MAXIPL+1];
238
239 char apic_level_intr[APIC_MAX_VECTOR+1];
240
241 uint32_t eisa_level_intr_mask = 0;
242 /* At least MSB will be set if EISA bus */
243
244 int apic_pci_bus_total = 0;
245 uchar_t apic_single_pci_busid = 0;
246
247 /*
248 * airq_mutex protects additions to the apic_irq_table - the first
249 * pointer and any airq_nexts off of that one. It also protects
250 * apic_max_device_irq & apic_min_device_irq. It also guarantees
251 * that share_id is unique as new ids are generated only when new
252 * irq_t structs are linked in. Once linked in the structs are never
253 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
254 * or allocated. Note that there is a slight gap between allocating in
255 * apic_introp_xlate and programming in addspl.
256 */
257 kmutex_t airq_mutex;
258 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
259 int apic_max_device_irq = 0;
260 int apic_min_device_irq = APIC_MAX_VECTOR;
261
262 typedef struct prs_irq_list_ent {
263 int list_prio;
264 int32_t irq;
265 iflag_t intrflags;
266 acpi_prs_private_t prsprv;
267 struct prs_irq_list_ent *next;
268 } prs_irq_list_t;
269
270
271 /*
272 * ACPI variables
273 */
274 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
275 int apic_enable_acpi = 0;
276
277 /* ACPI Multiple APIC Description Table ptr */
278 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
279
280 /* ACPI Interrupt Source Override Structure ptr */
281 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
282 int acpi_iso_cnt = 0;
283
284 /* ACPI Non-maskable Interrupt Sources ptr */
285 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
286 static int acpi_nmi_scnt = 0;
287 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
288 static int acpi_nmi_ccnt = 0;
289
290 static boolean_t acpi_found_smp_config = B_FALSE;
291
292 /*
293 * The following added to identify a software poweroff method if available.
294 */
295
296 static struct {
297 int poweroff_method;
298 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
299 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
300 } apic_mps_ids[] = {
301 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
302 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
303 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
306 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
308 };
309
310 int apic_poweroff_method = APIC_POWEROFF_NONE;
311
312 /*
313 * Auto-configuration routines
314 */
315
316 /*
317 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
318 * May work with 1.1 - but not guaranteed.
319 * According to the MP Spec, the MP floating pointer structure
320 * will be searched in the order described below:
321 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
322 * 2. Within the last kilobyte of system base memory
323 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
324 * Once we find the right signature with proper checksum, we call
325 * either handle_defconf or parse_mpct to get all info necessary for
326 * subsequent operations.
327 */
328 int
329 apic_probe_common(char *modname)
330 {
331 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
332 caddr_t biosdatap;
333 caddr_t mpct = 0;
334 caddr_t fptr;
335 int i, mpct_size, mapsize, retval = PSM_FAILURE;
336 ushort_t ebda_seg, base_mem_size;
337 struct apic_mpfps_hdr *fpsp;
338 struct apic_mp_cnf_hdr *hdrp;
339 int bypass_cpu_and_ioapics_in_mptables;
340 int acpi_user_options;
341
342 if (apic_forceload < 0)
343 return (retval);
344
345 /*
346 * Remember who we are
347 */
348 psm_name = modname;
349
350 /* Allow override for MADT-only mode */
351 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
352 "acpi-user-options", 0);
353 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
354
355 /* Allow apic_use_acpi to override MADT-only mode */
356 if (!apic_use_acpi)
357 apic_use_acpi_madt_only = 0;
358
359 retval = acpi_probe(modname);
360
361 /* in UEFI system, there is no BIOS data */
362 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab"))
363 goto apic_ret;
364
365 /*
366 * mapin the bios data area 40:0
367 * 40:13h - two-byte location reports the base memory size
368 * 40:0Eh - two-byte location for the exact starting address of
369 * the EBDA segment for EISA
370 */
371 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
372 if (!biosdatap)
373 goto apic_ret;
374 fpsp = (struct apic_mpfps_hdr *)NULL;
375 mapsize = MPFPS_RAM_WIN_LEN;
376 /*LINTED: pointer cast may result in improper alignment */
377 ebda_seg = *((ushort_t *)(biosdatap+0xe));
378 /* check the 1k of EBDA */
379 if (ebda_seg) {
380 ebda_start = ((uint32_t)ebda_seg) << 4;
381 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
382 if (fptr) {
383 if (!(fpsp =
384 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
385 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
386 }
387 }
388 /* If not in EBDA, check the last k of system base memory */
389 if (!fpsp) {
390 /*LINTED: pointer cast may result in improper alignment */
391 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
392
393 if (base_mem_size > 512)
394 base_mem_end = 639 * 1024;
395 else
396 base_mem_end = 511 * 1024;
397 /* if ebda == last k of base mem, skip to check BIOS ROM */
398 if (base_mem_end != ebda_start) {
399
400 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
401 PROT_READ);
402
403 if (fptr) {
404 if (!(fpsp = apic_find_fps_sig(fptr,
405 MPFPS_RAM_WIN_LEN)))
406 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
407 }
408 }
409 }
410 psm_unmap_phys(biosdatap, 0x20);
411
412 /* If still cannot find it, check the BIOS ROM space */
413 if (!fpsp) {
414 mapsize = MPFPS_ROM_WIN_LEN;
415 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
416 MPFPS_ROM_WIN_LEN, PROT_READ);
417 if (fptr) {
418 if (!(fpsp =
419 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
420 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
421 goto apic_ret;
422 }
423 }
424 }
425
426 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
427 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
428 goto apic_ret;
429 }
430
431 apic_spec_rev = fpsp->mpfps_spec_rev;
432 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
433 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
434 goto apic_ret;
435 }
436
437 /* check IMCR is present or not */
438 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
439
440 /* check default configuration (dual CPUs) */
441 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
442 psm_unmap_phys(fptr, mapsize);
443 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
444 return (retval);
445
446 goto apic_ret;
447 }
448
449 /* MP Configuration Table */
450 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
451
452 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
453
454 /*
455 * Map in enough memory for the MP Configuration Table Header.
456 * Use this table to read the total length of the BIOS data and
457 * map in all the info
458 */
459 /*LINTED: pointer cast may result in improper alignment */
460 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
461 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
462 if (!hdrp)
463 goto apic_ret;
464
465 /* check mp configuration table signature PCMP */
466 if (hdrp->mpcnf_sig != 0x504d4350) {
467 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
468 goto apic_ret;
469 }
470 mpct_size = (int)hdrp->mpcnf_tbl_length;
471
472 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
473
474 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
475
476 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
477 /* This is an ACPI machine No need for further checks */
478 goto apic_ret;
479 }
480
481 /*
482 * Map in the entries for this machine, ie. Processor
483 * Entry Tables, Bus Entry Tables, etc.
484 * They are in fixed order following one another
485 */
486 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
487 if (!mpct)
488 goto apic_ret;
489
490 if (apic_checksum(mpct, mpct_size) != 0)
491 goto apic_fail1;
492
493 /*LINTED: pointer cast may result in improper alignment */
494 hdrp = (struct apic_mp_cnf_hdr *)mpct;
495 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
496 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
497 if (!apicadr)
498 goto apic_fail1;
499
500 /* Parse all information in the tables */
501 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
502 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
503 PSM_SUCCESS) {
504 retval = PSM_SUCCESS;
505 goto apic_ret;
506 }
507
508 apic_fail1:
509 psm_unmap_phys(mpct, mpct_size);
510 mpct = NULL;
511
512 apic_ret:
513 if (retval == PSM_SUCCESS) {
514 extern int apic_ioapic_method_probe();
515
516 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
517 return (PSM_SUCCESS);
518 }
519
520 for (i = 0; i < apic_io_max; i++)
521 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
522 if (apic_cpus) {
523 kmem_free(apic_cpus, apic_cpus_size);
524 apic_cpus = NULL;
525 }
526 if (apicadr) {
527 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
528 apicadr = NULL;
529 }
530 if (mpct)
531 psm_unmap_phys(mpct, mpct_size);
532
533 return (retval);
534 }
535
536 static void
537 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
538 {
539 int i;
540
541 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
542 i++) {
543 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
544 strlen(apic_mps_ids[i].oem_id)) == 0) &&
545 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
546 strlen(apic_mps_ids[i].prod_id)) == 0)) {
547
548 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
549 break;
550 }
551 }
552
553 if (apic_debug_mps_id != 0) {
554 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
555 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
556 psm_name,
557 hdrp->mpcnf_oem_str[0],
558 hdrp->mpcnf_oem_str[1],
559 hdrp->mpcnf_oem_str[2],
560 hdrp->mpcnf_oem_str[3],
561 hdrp->mpcnf_oem_str[4],
562 hdrp->mpcnf_oem_str[5],
563 hdrp->mpcnf_oem_str[6],
564 hdrp->mpcnf_oem_str[7],
565 hdrp->mpcnf_prod_str[0],
566 hdrp->mpcnf_prod_str[1],
567 hdrp->mpcnf_prod_str[2],
568 hdrp->mpcnf_prod_str[3],
569 hdrp->mpcnf_prod_str[4],
570 hdrp->mpcnf_prod_str[5],
571 hdrp->mpcnf_prod_str[6],
572 hdrp->mpcnf_prod_str[7],
573 hdrp->mpcnf_prod_str[8],
574 hdrp->mpcnf_prod_str[9],
575 hdrp->mpcnf_prod_str[10],
576 hdrp->mpcnf_prod_str[11]);
577 }
578 }
579
580 static void
581 apic_free_apic_cpus(void)
582 {
583 if (apic_cpus != NULL) {
584 kmem_free(apic_cpus, apic_cpus_size);
585 apic_cpus = NULL;
586 apic_cpus_size = 0;
587 }
588 }
589
590 static int
591 acpi_probe(char *modname)
592 {
593 int i, intmax, index;
594 uint32_t id, ver;
595 int acpi_verboseflags = 0;
596 int madt_seen, madt_size;
597 ACPI_SUBTABLE_HEADER *ap;
598 ACPI_MADT_LOCAL_APIC *mpa;
599 ACPI_MADT_LOCAL_X2APIC *mpx2a;
600 ACPI_MADT_IO_APIC *mia;
601 ACPI_MADT_IO_SAPIC *misa;
602 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
603 ACPI_MADT_NMI_SOURCE *mns;
604 ACPI_MADT_INTERRUPT_SOURCE *mis;
605 ACPI_MADT_LOCAL_APIC_NMI *mlan;
606 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
607 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
608 int sci;
609 iflag_t sci_flags;
610 volatile uint32_t *ioapic;
611 int ioapic_ix;
612 uint32_t *local_ids;
613 uint32_t *proc_ids;
614 uchar_t hid;
615 int warned = 0;
616
617 if (!apic_use_acpi)
618 return (PSM_FAILURE);
619
620 if (AcpiGetTable(ACPI_SIG_MADT, 1,
621 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
622 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
623 return (PSM_FAILURE);
624 }
625
626 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
627 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
628 if (!apicadr)
629 return (PSM_FAILURE);
630
631 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
632 KM_NOSLEEP)) == NULL)
633 return (PSM_FAILURE);
634
635 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
636 KM_NOSLEEP)) == NULL) {
637 kmem_free(local_ids, NCPU * sizeof (uint32_t));
638 return (PSM_FAILURE);
639 }
640
641 id = apic_reg_ops->apic_read(APIC_LID_REG);
642 local_ids[0] = (uchar_t)(id >> 24);
643 apic_nproc = index = 1;
644 apic_io_max = 0;
645
646 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
647 madt_size = acpi_mapic_dtp->Header.Length;
648 madt_seen = sizeof (*acpi_mapic_dtp);
649
650 while (madt_seen < madt_size) {
651 switch (ap->Type) {
652 case ACPI_MADT_TYPE_LOCAL_APIC:
653 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
654 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
655 if (mpa->Id == 255) {
656 cmn_err(CE_WARN, "!%s: encountered "
657 "invalid entry in MADT: CPU %d "
658 "has Local APIC Id equal to 255 ",
659 psm_name, mpa->ProcessorId);
660 }
661 if (mpa->Id == local_ids[0]) {
662 ASSERT(index == 1);
663 proc_ids[0] = mpa->ProcessorId;
664 } else if (apic_nproc < NCPU && use_mp &&
665 apic_nproc < boot_ncpus) {
666 local_ids[index] = mpa->Id;
667 proc_ids[index] = mpa->ProcessorId;
668 index++;
669 apic_nproc++;
670 } else if (apic_nproc == NCPU && !warned) {
671 cmn_err(CE_WARN, "%s: CPU limit "
672 "exceeded"
673 #if !defined(__amd64)
674 " for 32-bit mode"
675 #endif
676 "; Solaris will use %d CPUs.",
677 psm_name, NCPU);
678 warned = 1;
679 }
680 }
681 break;
682
683 case ACPI_MADT_TYPE_IO_APIC:
684 mia = (ACPI_MADT_IO_APIC *) ap;
685 if (apic_io_max < MAX_IO_APIC) {
686 ioapic_ix = apic_io_max;
687 apic_io_id[apic_io_max] = mia->Id;
688 apic_io_vectbase[apic_io_max] =
689 mia->GlobalIrqBase;
690 apic_physaddr[apic_io_max] =
691 (uint32_t)mia->Address;
692 ioapic = apicioadr[apic_io_max] =
693 mapin_ioapic((uint32_t)mia->Address,
694 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
695 if (!ioapic)
696 goto cleanup;
697 ioapic_mask_workaround[apic_io_max] =
698 apic_is_ioapic_AMD_813x(mia->Address);
699 apic_io_max++;
700 }
701 break;
702
703 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
704 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
705 if (acpi_isop == NULL)
706 acpi_isop = mio;
707 acpi_iso_cnt++;
708 break;
709
710 case ACPI_MADT_TYPE_NMI_SOURCE:
711 /* UNIMPLEMENTED */
712 mns = (ACPI_MADT_NMI_SOURCE *) ap;
713 if (acpi_nmi_sp == NULL)
714 acpi_nmi_sp = mns;
715 acpi_nmi_scnt++;
716
717 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
718 mns->GlobalIrq, mns->IntiFlags);
719 break;
720
721 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
722 /* UNIMPLEMENTED */
723 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
724 if (acpi_nmi_cp == NULL)
725 acpi_nmi_cp = mlan;
726 acpi_nmi_ccnt++;
727
728 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
729 mlan->ProcessorId, mlan->IntiFlags,
730 mlan->Lint);
731 break;
732
733 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
734 /* UNIMPLEMENTED */
735 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
736 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
737 (long)mao->Address);
738 break;
739
740 case ACPI_MADT_TYPE_IO_SAPIC:
741 /* UNIMPLEMENTED */
742 misa = (ACPI_MADT_IO_SAPIC *) ap;
743
744 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
745 misa->Id, misa->GlobalIrqBase,
746 (long)misa->Address);
747 break;
748
749 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
750 /* UNIMPLEMENTED */
751 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
752
753 cmn_err(CE_NOTE,
754 "!apic: irq source: %d %d %d 0x%x %d %d\n",
755 mis->Id, mis->Eid, mis->GlobalIrq,
756 mis->IntiFlags, mis->Type,
757 mis->IoSapicVector);
758 break;
759
760 case ACPI_MADT_TYPE_LOCAL_X2APIC:
761 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
762
763 /*
764 * All logical processors with APIC ID values
765 * of 255 and greater will have their APIC
766 * reported through Processor X2APIC structure.
767 * All logical processors with APIC ID less than
768 * 255 will have their APIC reported through
769 * Processor Local APIC.
770 *
771 * Some systems apparently don't care and report all
772 * processors through Processor X2APIC structures. We
773 * warn about that but don't ignore those CPUs.
774 */
775 if (mpx2a->LocalApicId < 255) {
776 cmn_err(CE_WARN, "!%s: ignoring invalid entry "
777 "in MADT: CPU %d has X2APIC Id %d (< 255)",
778 psm_name, mpx2a->Uid, mpx2a->LocalApicId);
779 }
780 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
781 if (mpx2a->LocalApicId == local_ids[0]) {
782 ASSERT(index == 1);
783 proc_ids[0] = mpx2a->Uid;
784 } else if (apic_nproc < NCPU && use_mp &&
785 apic_nproc < boot_ncpus) {
786 local_ids[index] = mpx2a->LocalApicId;
787 proc_ids[index] = mpx2a->Uid;
788 index++;
789 apic_nproc++;
790 } else if (apic_nproc == NCPU && !warned) {
791 cmn_err(CE_WARN, "%s: CPU limit "
792 "exceeded"
793 #if !defined(__amd64)
794 " for 32-bit mode"
795 #endif
796 "; Solaris will use %d CPUs.",
797 psm_name, NCPU);
798 warned = 1;
799 }
800 }
801
802 break;
803
804 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
805 /* UNIMPLEMENTED */
806 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
807 if (mx2alan->Uid >> 8)
808 acpi_nmi_ccnt++;
809
810 #ifdef DEBUG
811 cmn_err(CE_NOTE,
812 "!apic: local x2apic nmi: %d 0x%x %d\n",
813 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
814 #endif
815
816 break;
817
818 case ACPI_MADT_TYPE_RESERVED:
819 default:
820 break;
821 }
822
823 /* advance to next entry */
824 madt_seen += ap->Length;
825 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
826 }
827
828 /* We found multiple enabled cpus via MADT */
829 if ((apic_nproc > 1) && (apic_io_max > 0)) {
830 acpi_found_smp_config = B_TRUE;
831 cmn_err(CE_NOTE,
832 "!apic: Using ACPI (MADT) for SMP configuration");
833 }
834
835 /*
836 * allocate enough space for possible hot-adding of CPUs.
837 * max_ncpus may be less than apic_nproc if it's set by user.
838 */
839 if (plat_dr_support_cpu()) {
840 apic_max_nproc = max_ncpus;
841 }
842 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
843 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
844 goto cleanup;
845
846 /*
847 * ACPI doesn't provide the local apic ver, get it directly from the
848 * local apic
849 */
850 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
851 for (i = 0; i < apic_nproc; i++) {
852 apic_cpus[i].aci_local_id = local_ids[i];
853 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
854 apic_cpus[i].aci_processor_id = proc_ids[i];
855 /* Only build mapping info for CPUs present at boot. */
856 if (i < boot_ncpus)
857 (void) acpica_map_cpu(i, proc_ids[i]);
858 }
859
860 /*
861 * To support CPU dynamic reconfiguration, the apic CPU info structure
862 * for each possible CPU will be pre-allocated at boot time.
863 * The state for each apic CPU info structure will be assigned according
864 * to the following rules:
865 * Rule 1:
866 * Slot index range: [0, min(apic_nproc, boot_ncpus))
867 * State flags: 0
868 * Note: cpu exists and will be configured/enabled at boot time
869 * Rule 2:
870 * Slot index range: [boot_ncpus, apic_nproc)
871 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
872 * Note: cpu exists but won't be configured/enabled at boot time
873 * Rule 3:
874 * Slot index range: [apic_nproc, boot_ncpus)
875 * State flags: APIC_CPU_FREE
876 * Note: cpu doesn't exist at boot time
877 * Rule 4:
878 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
879 * State flags: APIC_CPU_FREE
880 * Note: cpu doesn't exist at boot time
881 */
882 CPUSET_ZERO(apic_cpumask);
883 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
884 CPUSET_ADD(apic_cpumask, i);
885 apic_cpus[i].aci_status = 0;
886 }
887 for (i = boot_ncpus; i < apic_nproc; i++) {
888 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
889 }
890 for (i = apic_nproc; i < boot_ncpus; i++) {
891 apic_cpus[i].aci_status = APIC_CPU_FREE;
892 }
893 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
894 apic_cpus[i].aci_status = APIC_CPU_FREE;
895 }
896
897 for (i = 0; i < apic_io_max; i++) {
898 ioapic_ix = i;
899
900 /*
901 * need to check Sitka on the following acpi problem
902 * On the Sitka, the ioapic's apic_id field isn't reporting
903 * the actual io apic id. We have reported this problem
904 * to Intel. Until they fix the problem, we will get the
905 * actual id directly from the ioapic.
906 */
907 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
908 hid = (uchar_t)(id >> 24);
909
910 if (hid != apic_io_id[i]) {
911 if (apic_io_id[i] == 0)
912 apic_io_id[i] = hid;
913 else { /* set ioapic id to whatever reported by ACPI */
914 id = ((uint32_t)apic_io_id[i]) << 24;
915 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
916 }
917 }
918 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
919 apic_io_ver[i] = (uchar_t)(ver & 0xff);
920 intmax = (ver >> 16) & 0xff;
921 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
922 if (apic_first_avail_irq <= apic_io_vectend[i])
923 apic_first_avail_irq = apic_io_vectend[i] + 1;
924 }
925
926
927 /*
928 * Process SCI configuration here
929 * An error may be returned here if
930 * acpi-user-options specifies legacy mode
931 * (no SCI, no ACPI mode)
932 */
933 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
934 sci = -1;
935
936 /*
937 * Now call acpi_init() to generate namespaces
938 * If this fails, we don't attempt to use ACPI
939 * even if we were able to get a MADT above
940 */
941 if (acpica_init() != AE_OK) {
942 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
943 goto cleanup;
944 }
945
946 /*
947 * Call acpica_build_processor_map() now that we have
948 * ACPI namesspace access
949 */
950 (void) acpica_build_processor_map();
951
952 /*
953 * Squirrel away the SCI and flags for later on
954 * in apic_picinit() when we're ready
955 */
956 apic_sci_vect = sci;
957 apic_sci_flags = sci_flags;
958
959 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
960 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
961
962 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
963 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
964
965 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
966 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
967
968 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
969 goto cleanup;
970
971 /* Enable ACPI APIC interrupt routing */
972 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
973 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
974 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
975 apic_enable_acpi = 1;
976 if (apic_sci_vect > 0) {
977 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
978 }
979 if (apic_use_acpi_madt_only) {
980 cmn_err(CE_CONT,
981 "?Using ACPI for CPU/IOAPIC information ONLY\n");
982 }
983
984 #if !defined(__xpv)
985 /*
986 * probe ACPI for hpet information here which is used later
987 * in apic_picinit().
988 */
989 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
990 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
991 }
992 #endif
993
994 kmem_free(local_ids, NCPU * sizeof (uint32_t));
995 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
996 return (PSM_SUCCESS);
997 }
998 /* if setting APIC mode failed above, we fall through to cleanup */
999
1000 cleanup:
1001 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
1002 acpi_found_smp_config ? "found" : "not found");
1003 apic_free_apic_cpus();
1004 if (apicadr != NULL) {
1005 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1006 apicadr = NULL;
1007 }
1008 apic_max_nproc = -1;
1009 apic_nproc = 0;
1010 for (i = 0; i < apic_io_max; i++) {
1011 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
1012 apicioadr[i] = NULL;
1013 }
1014 apic_io_max = 0;
1015 acpi_isop = NULL;
1016 acpi_iso_cnt = 0;
1017 acpi_nmi_sp = NULL;
1018 acpi_nmi_scnt = 0;
1019 acpi_nmi_cp = NULL;
1020 acpi_nmi_ccnt = 0;
1021 acpi_found_smp_config = B_FALSE;
1022 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1023 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1024 return (PSM_FAILURE);
1025 }
1026
1027 /*
1028 * Handle default configuration. Fill in reqd global variables & tables
1029 * Fill all details as MP table does not give any more info
1030 */
1031 static int
1032 apic_handle_defconf()
1033 {
1034 uint_t lid;
1035
1036 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1037 apic_max_nproc = -1;
1038 apic_free_apic_cpus();
1039 plat_dr_disable_cpu();
1040
1041 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1042 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1043 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1044 APIC_LOCAL_MEMLEN, PROT_READ);
1045 apic_cpus_size = 2 * sizeof (*apic_cpus);
1046 apic_cpus = (apic_cpus_info_t *)
1047 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1048 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1049 goto apic_handle_defconf_fail;
1050 CPUSET_ONLY(apic_cpumask, 0);
1051 CPUSET_ADD(apic_cpumask, 1);
1052 apic_nproc = 2;
1053 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1054 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1055 /*
1056 * According to the PC+MP spec 1.1, the local ids
1057 * for the default configuration has to be 0 or 1
1058 */
1059 if (apic_cpus[0].aci_local_id == 1)
1060 apic_cpus[1].aci_local_id = 0;
1061 else if (apic_cpus[0].aci_local_id == 0)
1062 apic_cpus[1].aci_local_id = 1;
1063 else
1064 goto apic_handle_defconf_fail;
1065
1066 apic_io_id[0] = 2;
1067 apic_io_max = 1;
1068 if (apic_defconf >= 5) {
1069 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1070 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1071 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1072 } else {
1073 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1074 apic_cpus[1].aci_local_ver = 0;
1075 apic_io_ver[0] = 0;
1076 }
1077 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1078 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1079 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1080 return (PSM_SUCCESS);
1081
1082 apic_handle_defconf_fail:
1083 if (apicadr)
1084 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1085 if (apicioadr[0])
1086 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1087 return (PSM_FAILURE);
1088 }
1089
1090 /* Parse the entries in MP configuration table and collect info that we need */
1091 static int
1092 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1093 {
1094 struct apic_procent *procp;
1095 struct apic_bus *busp;
1096 struct apic_io_entry *ioapicp;
1097 struct apic_io_intr *intrp;
1098 int ioapic_ix;
1099 uint_t lid;
1100 uint32_t id;
1101 uchar_t hid;
1102 int warned = 0;
1103
1104 /*LINTED: pointer cast may result in improper alignment */
1105 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1106
1107 /* No need to count cpu entries if we won't use them */
1108 if (!bypass_cpus_and_ioapics) {
1109
1110 /* Find max # of CPUS and allocate structure accordingly */
1111 apic_nproc = 0;
1112 CPUSET_ZERO(apic_cpumask);
1113 while (procp->proc_entry == APIC_CPU_ENTRY) {
1114 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1115 if (apic_nproc < NCPU && use_mp &&
1116 apic_nproc < boot_ncpus) {
1117 CPUSET_ADD(apic_cpumask, apic_nproc);
1118 apic_nproc++;
1119 } else if (apic_nproc == NCPU && !warned) {
1120 cmn_err(CE_WARN, "%s: CPU limit "
1121 "exceeded"
1122 #if !defined(__amd64)
1123 " for 32-bit mode"
1124 #endif
1125 "; Solaris will use %d CPUs.",
1126 psm_name, NCPU);
1127 warned = 1;
1128 }
1129
1130 }
1131 procp++;
1132 }
1133 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1134 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1135 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1136 return (PSM_FAILURE);
1137 }
1138
1139 /*LINTED: pointer cast may result in improper alignment */
1140 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1141
1142 /*
1143 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1144 * if we're bypassing this information, it has already been filled
1145 * in by acpi_probe(), so don't overwrite it.
1146 */
1147 if (!bypass_cpus_and_ioapics)
1148 apic_nproc = 1;
1149
1150 while (procp->proc_entry == APIC_CPU_ENTRY) {
1151 /* check whether the cpu exists or not */
1152 if (!bypass_cpus_and_ioapics &&
1153 procp->proc_cpuflags & CPUFLAGS_EN) {
1154 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1155 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1156 apic_cpus[0].aci_local_id = procp->proc_apicid;
1157 if (apic_cpus[0].aci_local_id !=
1158 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1159 return (PSM_FAILURE);
1160 }
1161 apic_cpus[0].aci_local_ver =
1162 procp->proc_version;
1163 } else if (apic_nproc < NCPU && use_mp &&
1164 apic_nproc < boot_ncpus) {
1165 apic_cpus[apic_nproc].aci_local_id =
1166 procp->proc_apicid;
1167
1168 apic_cpus[apic_nproc].aci_local_ver =
1169 procp->proc_version;
1170 apic_nproc++;
1171
1172 }
1173 }
1174 procp++;
1175 }
1176
1177 /*
1178 * Save start of bus entries for later use.
1179 * Get EISA level cntrl if EISA bus is present.
1180 * Also get the CPI bus id for single CPI bus case
1181 */
1182 apic_busp = busp = (struct apic_bus *)procp;
1183 while (busp->bus_entry == APIC_BUS_ENTRY) {
1184 lid = apic_find_bus_type((char *)&busp->bus_str1);
1185 if (lid == BUS_EISA) {
1186 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1187 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1188 } else if (lid == BUS_PCI) {
1189 /*
1190 * apic_single_pci_busid will be used only if
1191 * apic_pic_bus_total is equal to 1
1192 */
1193 apic_pci_bus_total++;
1194 apic_single_pci_busid = busp->bus_id;
1195 }
1196 busp++;
1197 }
1198
1199 ioapicp = (struct apic_io_entry *)busp;
1200
1201 if (!bypass_cpus_and_ioapics)
1202 apic_io_max = 0;
1203 do {
1204 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1205 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1206 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1207 apic_io_ver[apic_io_max] = ioapicp->io_version;
1208 apicioadr[apic_io_max] =
1209 (void *)mapin_ioapic(
1210 (uint32_t)ioapicp->io_apic_addr,
1211 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1212
1213 if (!apicioadr[apic_io_max])
1214 return (PSM_FAILURE);
1215
1216 ioapic_mask_workaround[apic_io_max] =
1217 apic_is_ioapic_AMD_813x(
1218 ioapicp->io_apic_addr);
1219
1220 ioapic_ix = apic_io_max;
1221 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1222 hid = (uchar_t)(id >> 24);
1223
1224 if (hid != apic_io_id[apic_io_max]) {
1225 if (apic_io_id[apic_io_max] == 0)
1226 apic_io_id[apic_io_max] = hid;
1227 else {
1228 /*
1229 * set ioapic id to whatever
1230 * reported by MPS
1231 *
1232 * may not need to set index
1233 * again ???
1234 * take it out and try
1235 */
1236
1237 id = ((uint32_t)
1238 apic_io_id[apic_io_max]) <<
1239 24;
1240
1241 ioapic_write(ioapic_ix,
1242 APIC_ID_CMD, id);
1243 }
1244 }
1245 apic_io_max++;
1246 }
1247 }
1248 ioapicp++;
1249 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1250
1251 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1252
1253 intrp = apic_io_intrp;
1254 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1255 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1256 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1257 apic_irq_translate = 1;
1258 break;
1259 }
1260 intrp++;
1261 }
1262
1263 return (PSM_SUCCESS);
1264 }
1265
1266 boolean_t
1267 apic_cpu_in_range(int cpu)
1268 {
1269 cpu &= ~IRQ_USER_BOUND;
1270 /* Check whether cpu id is in valid range. */
1271 if (cpu < 0 || cpu >= apic_nproc) {
1272 return (B_FALSE);
1273 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1274 /*
1275 * Check whether cpuid is in valid range if CPU DR is enabled.
1276 */
1277 return (B_FALSE);
1278 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1279 return (B_FALSE);
1280 }
1281
1282 return (B_TRUE);
1283 }
1284
1285 processorid_t
1286 apic_get_next_bind_cpu(void)
1287 {
1288 int i, count;
1289 processorid_t cpuid = 0;
1290
1291 for (count = 0; count < apic_nproc; count++) {
1292 if (apic_next_bind_cpu >= apic_nproc) {
1293 apic_next_bind_cpu = 0;
1294 }
1295 i = apic_next_bind_cpu++;
1296 if (apic_cpu_in_range(i)) {
1297 cpuid = i;
1298 break;
1299 }
1300 }
1301
1302 return (cpuid);
1303 }
1304
1305 uint16_t
1306 apic_get_apic_version()
1307 {
1308 int i;
1309 uchar_t min_io_apic_ver = 0;
1310 static uint16_t version; /* Cache as value is constant */
1311 static boolean_t found = B_FALSE; /* Accomodate zero version */
1312
1313 if (found == B_FALSE) {
1314 found = B_TRUE;
1315
1316 /*
1317 * Don't assume all IO APICs in the system are the same.
1318 *
1319 * Set to the minimum version.
1320 */
1321 for (i = 0; i < apic_io_max; i++) {
1322 if ((apic_io_ver[i] != 0) &&
1323 ((min_io_apic_ver == 0) ||
1324 (min_io_apic_ver >= apic_io_ver[i])))
1325 min_io_apic_ver = apic_io_ver[i];
1326 }
1327
1328 /* Assume all local APICs are of the same version. */
1329 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1330 }
1331 return (version);
1332 }
1333
1334 static struct apic_mpfps_hdr *
1335 apic_find_fps_sig(caddr_t cptr, int len)
1336 {
1337 int i;
1338
1339 /* Look for the pattern "_MP_" */
1340 for (i = 0; i < len; i += 16) {
1341 if ((*(cptr+i) == '_') &&
1342 (*(cptr+i+1) == 'M') &&
1343 (*(cptr+i+2) == 'P') &&
1344 (*(cptr+i+3) == '_'))
1345 /*LINTED: pointer cast may result in improper alignment */
1346 return ((struct apic_mpfps_hdr *)(cptr + i));
1347 }
1348 return (NULL);
1349 }
1350
1351 static int
1352 apic_checksum(caddr_t bptr, int len)
1353 {
1354 int i;
1355 uchar_t cksum;
1356
1357 cksum = 0;
1358 for (i = 0; i < len; i++)
1359 cksum += *bptr++;
1360 return ((int)cksum);
1361 }
1362
1363 /*
1364 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1365 * needs special handling. We may need to chase up the device tree,
1366 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1367 * to find the IPIN at the root bus that relates to the IPIN on the
1368 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1369 * in the MP table or the ACPI namespace for this device itself.
1370 * We handle both cases in the search below.
1371 */
1372 /* this is the non-acpi version */
1373 int
1374 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1375 struct apic_io_intr **intrp)
1376 {
1377 dev_info_t *dipp, *dip;
1378 int pci_irq;
1379 ddi_acc_handle_t cfg_handle;
1380 int bridge_devno, bridge_bus;
1381 int ipin;
1382
1383 dip = idip;
1384
1385 /*CONSTCOND*/
1386 while (1) {
1387 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1388 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1389 return (-1);
1390 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1391 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1392 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1393 pci_config_teardown(&cfg_handle);
1394 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1395 NULL) != 0)
1396 return (-1);
1397 /*
1398 * This is the rotating scheme documented in the
1399 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1400 * behind another PCI-to-PCI bridge, then it needs
1401 * to keep ascending until an interrupt entry is
1402 * found or the root is reached.
1403 */
1404 ipin = (child_devno + child_ipin) % PCI_INTD;
1405 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1406 bridge_bus = (int)apic_single_pci_busid;
1407 pci_irq = ((bridge_devno & 0x1f) << 2) |
1408 (ipin & 0x3);
1409 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1410 bridge_bus)) != NULL) {
1411 return (pci_irq);
1412 }
1413 dip = dipp;
1414 child_devno = bridge_devno;
1415 child_ipin = ipin;
1416 } else {
1417 pci_config_teardown(&cfg_handle);
1418 return (-1);
1419 }
1420 }
1421 /*LINTED: function will not fall off the bottom */
1422 }
1423
1424 uchar_t
1425 acpi_find_ioapic(int irq)
1426 {
1427 int i;
1428
1429 for (i = 0; i < apic_io_max; i++) {
1430 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1431 return ((uchar_t)i);
1432 }
1433 return (0xFF); /* shouldn't happen */
1434 }
1435
1436 /*
1437 * See if two irqs are compatible for sharing a vector.
1438 * Currently we only support sharing of PCI devices.
1439 */
1440 static int
1441 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1442 {
1443 uint_t level1, po1;
1444 uint_t level2, po2;
1445
1446 /* Assume active high by default */
1447 po1 = 0;
1448 po2 = 0;
1449
1450 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1451 return (0);
1452
1453 if (iflag1.intr_el == INTR_EL_CONFORM)
1454 level1 = AV_LEVEL;
1455 else
1456 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1457
1458 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1459 (iflag1.intr_po == INTR_PO_CONFORM)))
1460 po1 = AV_ACTIVE_LOW;
1461
1462 if (iflag2.intr_el == INTR_EL_CONFORM)
1463 level2 = AV_LEVEL;
1464 else
1465 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1466
1467 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1468 (iflag2.intr_po == INTR_PO_CONFORM)))
1469 po2 = AV_ACTIVE_LOW;
1470
1471 if ((level1 == level2) && (po1 == po2))
1472 return (1);
1473
1474 return (0);
1475 }
1476
1477 struct apic_io_intr *
1478 apic_find_io_intr_w_busid(int irqno, int busid)
1479 {
1480 struct apic_io_intr *intrp;
1481
1482 /*
1483 * It can have more than 1 entry with same source bus IRQ,
1484 * but unique with the source bus id
1485 */
1486 intrp = apic_io_intrp;
1487 if (intrp != NULL) {
1488 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1489 if (intrp->intr_irq == irqno &&
1490 intrp->intr_busid == busid &&
1491 intrp->intr_type == IO_INTR_INT)
1492 return (intrp);
1493 intrp++;
1494 }
1495 }
1496 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1497 "busid %x:%x\n", irqno, busid));
1498 return ((struct apic_io_intr *)NULL);
1499 }
1500
1501
1502 struct mps_bus_info {
1503 char *bus_name;
1504 int bus_id;
1505 } bus_info_array[] = {
1506 "ISA ", BUS_ISA,
1507 "PCI ", BUS_PCI,
1508 "EISA ", BUS_EISA,
1509 "XPRESS", BUS_XPRESS,
1510 "PCMCIA", BUS_PCMCIA,
1511 "VL ", BUS_VL,
1512 "CBUS ", BUS_CBUS,
1513 "CBUSII", BUS_CBUSII,
1514 "FUTURE", BUS_FUTURE,
1515 "INTERN", BUS_INTERN,
1516 "MBI ", BUS_MBI,
1517 "MBII ", BUS_MBII,
1518 "MPI ", BUS_MPI,
1519 "MPSA ", BUS_MPSA,
1520 "NUBUS ", BUS_NUBUS,
1521 "TC ", BUS_TC,
1522 "VME ", BUS_VME,
1523 "PCI-E ", BUS_PCIE
1524 };
1525
1526 static int
1527 apic_find_bus_type(char *bus)
1528 {
1529 int i = 0;
1530
1531 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1532 if (strncmp(bus, bus_info_array[i].bus_name,
1533 strlen(bus_info_array[i].bus_name)) == 0)
1534 return (bus_info_array[i].bus_id);
1535 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1536 return (0);
1537 }
1538
1539 static int
1540 apic_find_bus(int busid)
1541 {
1542 struct apic_bus *busp;
1543
1544 busp = apic_busp;
1545 while (busp->bus_entry == APIC_BUS_ENTRY) {
1546 if (busp->bus_id == busid)
1547 return (apic_find_bus_type((char *)&busp->bus_str1));
1548 busp++;
1549 }
1550 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1551 return (0);
1552 }
1553
1554 int
1555 apic_find_bus_id(int bustype)
1556 {
1557 struct apic_bus *busp;
1558
1559 busp = apic_busp;
1560 while (busp->bus_entry == APIC_BUS_ENTRY) {
1561 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1562 return (busp->bus_id);
1563 busp++;
1564 }
1565 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1566 bustype));
1567 return (-1);
1568 }
1569
1570 /*
1571 * Check if a particular irq need to be reserved for any io_intr
1572 */
1573 static struct apic_io_intr *
1574 apic_find_io_intr(int irqno)
1575 {
1576 struct apic_io_intr *intrp;
1577
1578 intrp = apic_io_intrp;
1579 if (intrp != NULL) {
1580 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1581 if (intrp->intr_irq == irqno &&
1582 intrp->intr_type == IO_INTR_INT)
1583 return (intrp);
1584 intrp++;
1585 }
1586 }
1587 return ((struct apic_io_intr *)NULL);
1588 }
1589
1590 /*
1591 * Check if the given ioapicindex intin combination has already been assigned
1592 * an irq. If so return irqno. Else -1
1593 */
1594 int
1595 apic_find_intin(uchar_t ioapic, uchar_t intin)
1596 {
1597 apic_irq_t *irqptr;
1598 int i;
1599
1600 /* find ioapic and intin in the apic_irq_table[] and return the index */
1601 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1602 irqptr = apic_irq_table[i];
1603 while (irqptr) {
1604 if ((irqptr->airq_mps_intr_index >= 0) &&
1605 (irqptr->airq_intin_no == intin) &&
1606 (irqptr->airq_ioapicindex == ioapic)) {
1607 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1608 "entry for ioapic:intin %x:%x "
1609 "shared interrupts ?", ioapic, intin));
1610 return (i);
1611 }
1612 irqptr = irqptr->airq_next;
1613 }
1614 }
1615 return (-1);
1616 }
1617
1618 int
1619 apic_allocate_irq(int irq)
1620 {
1621 int freeirq, i;
1622
1623 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1624 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1625 (irq - 1))) == -1) {
1626 /*
1627 * if BIOS really defines every single irq in the mps
1628 * table, then don't worry about conflicting with
1629 * them, just use any free slot in apic_irq_table
1630 */
1631 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1632 if ((apic_irq_table[i] == NULL) ||
1633 apic_irq_table[i]->airq_mps_intr_index ==
1634 FREE_INDEX) {
1635 freeirq = i;
1636 break;
1637 }
1638 }
1639 if (freeirq == -1) {
1640 /* This shouldn't happen, but just in case */
1641 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1642 return (-1);
1643 }
1644 }
1645 if (apic_irq_table[freeirq] == NULL) {
1646 apic_irq_table[freeirq] =
1647 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1648 if (apic_irq_table[freeirq] == NULL) {
1649 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1650 psm_name);
1651 return (-1);
1652 }
1653 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1654 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1655 }
1656 return (freeirq);
1657 }
1658
1659 static int
1660 apic_find_free_irq(int start, int end)
1661 {
1662 int i;
1663
1664 for (i = start; i <= end; i++)
1665 /* Check if any I/O entry needs this IRQ */
1666 if (apic_find_io_intr(i) == NULL) {
1667 /* Then see if it is free */
1668 if ((apic_irq_table[i] == NULL) ||
1669 (apic_irq_table[i]->airq_mps_intr_index ==
1670 FREE_INDEX)) {
1671 return (i);
1672 }
1673 }
1674 return (-1);
1675 }
1676
1677 /*
1678 * compute the polarity, trigger mode and vector for programming into
1679 * the I/O apic and record in airq_rdt_entry.
1680 */
1681 void
1682 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1683 {
1684 int ioapicindex, bus_type, vector;
1685 short intr_index;
1686 uint_t level, po, io_po;
1687 struct apic_io_intr *iointrp;
1688
1689 intr_index = irqptr->airq_mps_intr_index;
1690 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1691 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1692 (void *)irqptr->airq_dip, irqptr->airq_vector));
1693
1694 if (intr_index == RESERVE_INDEX) {
1695 apic_error |= APIC_ERR_INVALID_INDEX;
1696 return;
1697 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1698 return;
1699 }
1700
1701 vector = irqptr->airq_vector;
1702 ioapicindex = irqptr->airq_ioapicindex;
1703 /* Assume edge triggered by default */
1704 level = 0;
1705 /* Assume active high by default */
1706 po = 0;
1707
1708 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1709 ASSERT(irq < 16);
1710 if (eisa_level_intr_mask & (1 << irq))
1711 level = AV_LEVEL;
1712 if (intr_index == FREE_INDEX && apic_defconf == 0)
1713 apic_error |= APIC_ERR_INVALID_INDEX;
1714 } else if (intr_index == ACPI_INDEX) {
1715 bus_type = irqptr->airq_iflag.bustype;
1716 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1717 if (bus_type == BUS_PCI)
1718 level = AV_LEVEL;
1719 } else
1720 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1721 AV_LEVEL : 0;
1722 if (level &&
1723 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1724 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1725 bus_type == BUS_PCI)))
1726 po = AV_ACTIVE_LOW;
1727 } else {
1728 iointrp = apic_io_intrp + intr_index;
1729 bus_type = apic_find_bus(iointrp->intr_busid);
1730 if (iointrp->intr_el == INTR_EL_CONFORM) {
1731 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1732 level = AV_LEVEL;
1733 else if (bus_type == BUS_PCI)
1734 level = AV_LEVEL;
1735 } else
1736 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1737 AV_LEVEL : 0;
1738 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1739 (iointrp->intr_po == INTR_PO_CONFORM &&
1740 bus_type == BUS_PCI)))
1741 po = AV_ACTIVE_LOW;
1742 }
1743 if (level)
1744 apic_level_intr[irq] = 1;
1745 /*
1746 * The 82489DX External APIC cannot do active low polarity interrupts.
1747 */
1748 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1749 io_po = po;
1750 else
1751 io_po = 0;
1752
1753 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1754 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1755 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1756 irqptr->airq_intin_no, level, io_po, vector,
1757 irqptr->airq_cpu);
1758
1759 irqptr->airq_rdt_entry = level|io_po|vector;
1760 }
1761
1762 int
1763 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1764 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1765 {
1766
1767 int status;
1768 acpi_psm_lnk_t acpipsmlnk;
1769
1770 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1771 intr_flagp)) == ACPI_PSM_SUCCESS) {
1772 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1773 "from cache for device %s, instance #%d\n", psm_name,
1774 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1775 return (status);
1776 }
1777
1778 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1779
1780 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1781 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1782 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1783 " acpi_translate_pci_irq failed for device %s, instance"
1784 " #%d", psm_name, ddi_get_name(dip),
1785 ddi_get_instance(dip)));
1786 return (status);
1787 }
1788
1789 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1790 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1791 intr_flagp);
1792 if (status != ACPI_PSM_SUCCESS) {
1793 status = acpi_get_current_irq_resource(&acpipsmlnk,
1794 pci_irqp, intr_flagp);
1795 }
1796 }
1797
1798 if (status == ACPI_PSM_SUCCESS) {
1799 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1800 intr_flagp, &acpipsmlnk);
1801
1802 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1803 "new irq %d for device %s, instance #%d\n", psm_name,
1804 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1805 }
1806
1807 return (status);
1808 }
1809
1810 /*
1811 * Adds an entry to the irq list passed in, and returns the new list.
1812 * Entries are added in priority order (lower numerical priorities are
1813 * placed closer to the head of the list)
1814 */
1815 static prs_irq_list_t *
1816 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1817 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1818 {
1819 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1820
1821 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1822
1823 newent->list_prio = priority;
1824 newent->irq = irq;
1825 newent->intrflags = *iflagp;
1826 newent->prsprv = *prsprvp;
1827 /* ->next is NULL from kmem_zalloc */
1828
1829 /*
1830 * New list -- return the new entry as the list.
1831 */
1832 if (listp == NULL)
1833 return (newent);
1834
1835 /*
1836 * Save original list pointer for return (since we're not modifying
1837 * the head)
1838 */
1839 origlistp = listp;
1840
1841 /*
1842 * Insertion sort, with entries with identical keys stored AFTER
1843 * existing entries (the less-than-or-equal test of priority does
1844 * this for us).
1845 */
1846 while (listp != NULL && listp->list_prio <= priority) {
1847 prevp = listp;
1848 listp = listp->next;
1849 }
1850
1851 newent->next = listp;
1852
1853 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1854 return (newent);
1855 } else {
1856 prevp->next = newent;
1857 return (origlistp);
1858 }
1859 }
1860
1861 /*
1862 * Frees the list passed in, deallocating all memory and leaving *listpp
1863 * set to NULL.
1864 */
1865 static void
1866 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1867 {
1868 struct prs_irq_list_ent *nextp;
1869
1870 ASSERT(listpp != NULL);
1871
1872 while (*listpp != NULL) {
1873 nextp = (*listpp)->next;
1874 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1875 *listpp = nextp;
1876 }
1877 }
1878
1879 /*
1880 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1881 * irqs returned by the link device's _PRS method. The irqs are chosen
1882 * to minimize contention in situations where the interrupt link device
1883 * can be programmed to steer interrupts to different interrupt controller
1884 * inputs (some of which may already be in use). The list is sorted in order
1885 * of irqs to use, with the highest priority given to interrupt controller
1886 * inputs that are not shared. When an interrupt controller input
1887 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1888 * returned list in the order that minimizes sharing (thereby ensuring lowest
1889 * possible latency from interrupt trigger time to ISR execution time).
1890 */
1891 static prs_irq_list_t *
1892 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1893 int crs_irq)
1894 {
1895 int32_t irq;
1896 int i;
1897 prs_irq_list_t *prsirqlistp = NULL;
1898 iflag_t iflags;
1899
1900 while (irqlistent != NULL) {
1901 irqlistent->intr_flags.bustype = BUS_PCI;
1902
1903 for (i = 0; i < irqlistent->num_irqs; i++) {
1904
1905 irq = irqlistent->irqs[i];
1906
1907 if (irq <= 0) {
1908 /* invalid irq number */
1909 continue;
1910 }
1911
1912 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1913 continue;
1914
1915 if ((apic_irq_table[irq] == NULL) ||
1916 (apic_irq_table[irq]->airq_dip == dip)) {
1917
1918 prsirqlistp = acpi_insert_prs_irq_ent(
1919 prsirqlistp, 0 /* Highest priority */, irq,
1920 &irqlistent->intr_flags,
1921 &irqlistent->acpi_prs_prv);
1922
1923 /*
1924 * If we do not prefer the current irq from _CRS
1925 * or if we do and this irq is the same as the
1926 * current irq from _CRS, this is the one
1927 * to pick.
1928 */
1929 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1930 return (prsirqlistp);
1931 }
1932 continue;
1933 }
1934
1935 /*
1936 * Edge-triggered interrupts cannot be shared
1937 */
1938 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1939 continue;
1940
1941 /*
1942 * To work around BIOSes that contain incorrect
1943 * interrupt polarity information in interrupt
1944 * descriptors returned by _PRS, we assume that
1945 * the polarity of the other device sharing this
1946 * interrupt controller input is compatible.
1947 * If it's not, the caller will catch it when
1948 * the caller invokes the link device's _CRS method
1949 * (after invoking its _SRS method).
1950 */
1951 iflags = irqlistent->intr_flags;
1952 iflags.intr_po =
1953 apic_irq_table[irq]->airq_iflag.intr_po;
1954
1955 if (!acpi_intr_compatible(iflags,
1956 apic_irq_table[irq]->airq_iflag)) {
1957 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1958 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1959 psm_name, irq,
1960 iflags.intr_po,
1961 iflags.intr_el,
1962 iflags.bustype,
1963 apic_irq_table[irq]->airq_iflag.intr_po,
1964 apic_irq_table[irq]->airq_iflag.intr_el,
1965 apic_irq_table[irq]->airq_iflag.bustype));
1966 continue;
1967 }
1968
1969 /*
1970 * If we prefer the irq from _CRS, no need
1971 * to search any further (and make sure
1972 * to add this irq with the highest priority
1973 * so it's tried first).
1974 */
1975 if (crs_irq == irq && apic_prefer_crs) {
1976
1977 return (acpi_insert_prs_irq_ent(
1978 prsirqlistp,
1979 0 /* Highest priority */,
1980 irq, &iflags,
1981 &irqlistent->acpi_prs_prv));
1982 }
1983
1984 /*
1985 * Priority is equal to the share count (lower
1986 * share count is higher priority). Note that
1987 * the intr flags passed in here are the ones we
1988 * changed above -- if incorrect, it will be
1989 * caught by the caller's _CRS flags comparison.
1990 */
1991 prsirqlistp = acpi_insert_prs_irq_ent(
1992 prsirqlistp,
1993 apic_irq_table[irq]->airq_share, irq,
1994 &iflags, &irqlistent->acpi_prs_prv);
1995 }
1996
1997 /* Go to the next irqlist entry */
1998 irqlistent = irqlistent->next;
1999 }
2000
2001 return (prsirqlistp);
2002 }
2003
2004 /*
2005 * Configures the irq for the interrupt link device identified by
2006 * acpipsmlnkp.
2007 *
2008 * Gets the current and the list of possible irq settings for the
2009 * device. If apic_unconditional_srs is not set, and the current
2010 * resource setting is in the list of possible irq settings,
2011 * current irq resource setting is passed to the caller.
2012 *
2013 * Otherwise, picks an irq number from the list of possible irq
2014 * settings, and sets the irq of the device to this value.
2015 * If prefer_crs is set, among a set of irq numbers in the list that have
2016 * the least number of devices sharing the interrupt, we pick current irq
2017 * resource setting if it is a member of this set.
2018 *
2019 * Passes the irq number in the value pointed to by pci_irqp, and
2020 * polarity and sensitivity in the structure pointed to by dipintrflagp
2021 * to the caller.
2022 *
2023 * Note that if setting the irq resource failed, but successfuly obtained
2024 * the current irq resource settings, passes the current irq resources
2025 * and considers it a success.
2026 *
2027 * Returns:
2028 * ACPI_PSM_SUCCESS on success.
2029 *
2030 * ACPI_PSM_FAILURE if an error occured during the configuration or
2031 * if a suitable irq was not found for this device, or if setting the
2032 * irq resource and obtaining the current resource fails.
2033 *
2034 */
2035 static int
2036 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2037 int *pci_irqp, iflag_t *dipintr_flagp)
2038 {
2039 int32_t irq;
2040 int cur_irq = -1;
2041 acpi_irqlist_t *irqlistp;
2042 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2043 boolean_t found_irq = B_FALSE;
2044
2045 dipintr_flagp->bustype = BUS_PCI;
2046
2047 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2048 == ACPI_PSM_FAILURE) {
2049 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2050 "or assign IRQ for device %s, instance #%d: The system was "
2051 "unable to get the list of potential IRQs from ACPI.",
2052 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2053
2054 return (ACPI_PSM_FAILURE);
2055 }
2056
2057 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2058 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2059 (cur_irq > 0)) {
2060 /*
2061 * If an IRQ is set in CRS and that IRQ exists in the set
2062 * returned from _PRS, return that IRQ, otherwise print
2063 * a warning
2064 */
2065
2066 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2067 == ACPI_PSM_SUCCESS) {
2068
2069 ASSERT(pci_irqp != NULL);
2070 *pci_irqp = cur_irq;
2071 acpi_free_irqlist(irqlistp);
2072 return (ACPI_PSM_SUCCESS);
2073 }
2074
2075 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2076 "current irq %d for device %s, instance #%d in ACPI's "
2077 "list of possible irqs for this device. Picking one from "
2078 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2079 ddi_get_instance(dip)));
2080 }
2081
2082 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2083 cur_irq)) == NULL) {
2084
2085 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2086 "suitable irq from the list of possible irqs for device "
2087 "%s, instance #%d in ACPI's list of possible irqs",
2088 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2089
2090 acpi_free_irqlist(irqlistp);
2091 return (ACPI_PSM_FAILURE);
2092 }
2093
2094 acpi_free_irqlist(irqlistp);
2095
2096 for (prs_irq_entp = prs_irq_listp;
2097 prs_irq_entp != NULL && found_irq == B_FALSE;
2098 prs_irq_entp = prs_irq_entp->next) {
2099
2100 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2101 irq = prs_irq_entp->irq;
2102
2103 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2104 "device %s instance #%d\n", psm_name, irq,
2105 ddi_get_name(dip), ddi_get_instance(dip)));
2106
2107 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2108 == ACPI_PSM_SUCCESS) {
2109 /*
2110 * setting irq was successful, check to make sure CRS
2111 * reflects that. If CRS does not agree with what we
2112 * set, return the irq that was set.
2113 */
2114
2115 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2116 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2117
2118 if (cur_irq != irq)
2119 APIC_VERBOSE_IRQ((CE_WARN,
2120 "!%s: IRQ resource set "
2121 "(irqno %d) for device %s "
2122 "instance #%d, differs from "
2123 "current setting irqno %d",
2124 psm_name, irq, ddi_get_name(dip),
2125 ddi_get_instance(dip), cur_irq));
2126 } else {
2127 /*
2128 * On at least one system, there was a bug in
2129 * a DSDT method called by _STA, causing _STA to
2130 * indicate that the link device was disabled
2131 * (when, in fact, it was enabled). Since _SRS
2132 * succeeded, assume that _CRS is lying and use
2133 * the iflags from this _PRS interrupt choice.
2134 * If we're wrong about the flags, the polarity
2135 * will be incorrect and we may get an interrupt
2136 * storm, but there's not much else we can do
2137 * at this point.
2138 */
2139 *dipintr_flagp = prs_irq_entp->intrflags;
2140 }
2141
2142 /*
2143 * Return the irq that was set, and not what _CRS
2144 * reports, since _CRS has been seen to return
2145 * different IRQs than what was passed to _SRS on some
2146 * systems (and just not return successfully on others).
2147 */
2148 cur_irq = irq;
2149 found_irq = B_TRUE;
2150 } else {
2151 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2152 "irq %d failed for device %s instance #%d",
2153 psm_name, irq, ddi_get_name(dip),
2154 ddi_get_instance(dip)));
2155
2156 if (cur_irq == -1) {
2157 acpi_destroy_prs_irq_list(&prs_irq_listp);
2158 return (ACPI_PSM_FAILURE);
2159 }
2160 }
2161 }
2162
2163 acpi_destroy_prs_irq_list(&prs_irq_listp);
2164
2165 if (!found_irq)
2166 return (ACPI_PSM_FAILURE);
2167
2168 ASSERT(pci_irqp != NULL);
2169 *pci_irqp = cur_irq;
2170 return (ACPI_PSM_SUCCESS);
2171 }
2172
2173 void
2174 ioapic_disable_redirection()
2175 {
2176 int ioapic_ix;
2177 int intin_max;
2178 int intin_ix;
2179
2180 /* Disable the I/O APIC redirection entries */
2181 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2182
2183 /* Bits 23-16 define the maximum redirection entries */
2184 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2185 & 0xff;
2186
2187 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2188 /*
2189 * The assumption here is that this is safe, even for
2190 * systems with IOAPICs that suffer from the hardware
2191 * erratum because all devices have been quiesced before
2192 * this function is called from apic_shutdown()
2193 * (or equivalent). If that assumption turns out to be
2194 * false, this mask operation can induce the same
2195 * erratum result we're trying to avoid.
2196 */
2197 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2198 AV_MASK);
2199 }
2200 }
2201 }
2202
2203 /*
2204 * Looks for an IOAPIC with the specified physical address in the /ioapics
2205 * node in the device tree (created by the PCI enumerator).
2206 */
2207 static boolean_t
2208 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2209 {
2210 /*
2211 * Look in /ioapics, for the ioapic with
2212 * the physical address given
2213 */
2214 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2215 dev_info_t *ioapic_child;
2216 boolean_t rv = B_FALSE;
2217 int vid, did;
2218 uint64_t ioapic_paddr;
2219 boolean_t done = B_FALSE;
2220
2221 if (ioapicsnode == NULL)
2222 return (B_FALSE);
2223
2224 /* Load first child: */
2225 ioapic_child = ddi_get_child(ioapicsnode);
2226 while (!done && ioapic_child != 0) { /* Iterate over children */
2227
2228 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2229 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2230 != 0 && physaddr == ioapic_paddr) {
2231
2232 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2233 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2234
2235 if (vid == VENID_AMD) {
2236
2237 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2238 ioapic_child, DDI_PROP_DONTPASS,
2239 IOAPICS_PROP_DEVID, 0);
2240
2241 if (did == DEVID_8131_IOAPIC ||
2242 did == DEVID_8132_IOAPIC) {
2243 rv = B_TRUE;
2244 done = B_TRUE;
2245 }
2246 }
2247 }
2248
2249 if (!done)
2250 ioapic_child = ddi_get_next_sibling(ioapic_child);
2251 }
2252
2253 /* The ioapics node was held by ddi_find_devinfo, so release it */
2254 ndi_rele_devi(ioapicsnode);
2255 return (rv);
2256 }
2257
2258 struct apic_state {
2259 int32_t as_task_reg;
2260 int32_t as_dest_reg;
2261 int32_t as_format_reg;
2262 int32_t as_local_timer;
2263 int32_t as_pcint_vect;
2264 int32_t as_int_vect0;
2265 int32_t as_int_vect1;
2266 int32_t as_err_vect;
2267 int32_t as_init_count;
2268 int32_t as_divide_reg;
2269 int32_t as_spur_int_reg;
2270 uint32_t as_ioapic_ids[MAX_IO_APIC];
2271 };
2272
2273
2274 static int
2275 apic_acpi_enter_apicmode(void)
2276 {
2277 ACPI_OBJECT_LIST arglist;
2278 ACPI_OBJECT arg;
2279 ACPI_STATUS status;
2280
2281 /* Setup parameter object */
2282 arglist.Count = 1;
2283 arglist.Pointer = &arg;
2284 arg.Type = ACPI_TYPE_INTEGER;
2285 arg.Integer.Value = ACPI_APIC_MODE;
2286
2287 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2288 /*
2289 * Per ACPI spec - section 5.8.1 _PIC Method
2290 * calling the \_PIC control method is optional for the OS
2291 * and might not be found. It's ok to not fail in such cases.
2292 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2293 */
2294 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2295 cmn_err(CE_NOTE,
2296 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2297 ACPI_FAILURE(status));
2298 return (PSM_FAILURE);
2299 } else {
2300 return (PSM_SUCCESS);
2301 }
2302 }
2303
2304
2305 static void
2306 apic_save_state(struct apic_state *sp)
2307 {
2308 int i, cpuid;
2309 ulong_t iflag;
2310
2311 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2312 /*
2313 * First the local APIC.
2314 */
2315 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2316 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2317 if (apic_mode == LOCAL_APIC)
2318 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2319 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2320 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2321 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2322 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2323 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2324 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2325 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2326 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2327
2328 /*
2329 * If on the boot processor then save the IOAPICs' IDs
2330 */
2331 if ((cpuid = psm_get_cpu_id()) == 0) {
2332
2333 iflag = intr_clear();
2334 lock_set(&apic_ioapic_lock);
2335
2336 for (i = 0; i < apic_io_max; i++)
2337 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2338
2339 lock_clear(&apic_ioapic_lock);
2340 intr_restore(iflag);
2341 }
2342
2343 /* apic_state() is currently invoked only in Suspend/Resume */
2344 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2345 }
2346
2347 static void
2348 apic_restore_state(struct apic_state *sp)
2349 {
2350 int i;
2351 ulong_t iflag;
2352
2353 /*
2354 * First the local APIC.
2355 */
2356 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2357 if (apic_mode == LOCAL_APIC) {
2358 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2359 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2360 }
2361 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2362 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2363 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2364 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2365 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2366 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2367 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2368 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2369
2370 /*
2371 * the following only needs to be done once, so we do it on the
2372 * boot processor, since we know that we only have one of those
2373 */
2374 if (psm_get_cpu_id() == 0) {
2375
2376 iflag = intr_clear();
2377 lock_set(&apic_ioapic_lock);
2378
2379 /* Restore IOAPICs' APIC IDs */
2380 for (i = 0; i < apic_io_max; i++) {
2381 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2382 }
2383
2384 lock_clear(&apic_ioapic_lock);
2385 intr_restore(iflag);
2386
2387 /*
2388 * Reenter APIC mode before restoring LNK devices
2389 */
2390 (void) apic_acpi_enter_apicmode();
2391
2392 /*
2393 * restore acpi link device mappings
2394 */
2395 acpi_restore_link_devices();
2396 }
2397 }
2398
2399 /*
2400 * Returns 0 on success
2401 */
2402 int
2403 apic_state(psm_state_request_t *rp)
2404 {
2405 PMD(PMD_SX, ("apic_state "))
2406 switch (rp->psr_cmd) {
2407 case PSM_STATE_ALLOC:
2408 rp->req.psm_state_req.psr_state =
2409 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2410 if (rp->req.psm_state_req.psr_state == NULL)
2411 return (ENOMEM);
2412 rp->req.psm_state_req.psr_state_size =
2413 sizeof (struct apic_state);
2414 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2415 rp->req.psm_state_req.psr_state,
2416 rp->req.psm_state_req.psr_state_size))
2417 return (0);
2418
2419 case PSM_STATE_FREE:
2420 kmem_free(rp->req.psm_state_req.psr_state,
2421 rp->req.psm_state_req.psr_state_size);
2422 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2423 rp->req.psm_state_req.psr_state,
2424 rp->req.psm_state_req.psr_state_size))
2425 return (0);
2426
2427 case PSM_STATE_SAVE:
2428 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2429 rp->req.psm_state_req.psr_state,
2430 rp->req.psm_state_req.psr_state_size))
2431 apic_save_state(rp->req.psm_state_req.psr_state);
2432 return (0);
2433
2434 case PSM_STATE_RESTORE:
2435 apic_restore_state(rp->req.psm_state_req.psr_state);
2436 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2437 rp->req.psm_state_req.psr_state,
2438 rp->req.psm_state_req.psr_state_size))
2439 return (0);
2440
2441 default:
2442 return (EINVAL);
2443 }
2444 }