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8626 make pcplusmp and apix warning-free
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
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--- old/usr/src/uts/i86pc/io/mp_platform_common.c
+++ new/usr/src/uts/i86pc/io/mp_platform_common.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2016 Nexenta Systems, Inc.
24 24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 + * Copyright 2017 Joyent, Inc.
25 26 */
26 27 /*
27 28 * Copyright (c) 2010, Intel Corporation.
28 29 * All rights reserved.
29 30 */
30 31
31 32 /*
32 33 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
33 34 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
34 35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
35 36 * PSMI 1.5 extensions are supported in Solaris Nevada.
36 37 * PSMI 1.6 extensions are supported in Solaris Nevada.
37 38 * PSMI 1.7 extensions are supported in Solaris Nevada.
38 39 */
39 40 #define PSMI_1_7
40 41
41 42 #include <sys/processor.h>
42 43 #include <sys/time.h>
43 44 #include <sys/psm.h>
44 45 #include <sys/smp_impldefs.h>
45 46 #include <sys/cram.h>
46 47 #include <sys/acpi/acpi.h>
47 48 #include <sys/acpica.h>
48 49 #include <sys/psm_common.h>
49 50 #include <sys/apic.h>
50 51 #include <sys/apic_timer.h>
51 52 #include <sys/pit.h>
52 53 #include <sys/ddi.h>
53 54 #include <sys/sunddi.h>
54 55 #include <sys/ddi_impldefs.h>
55 56 #include <sys/pci.h>
56 57 #include <sys/promif.h>
57 58 #include <sys/x86_archext.h>
58 59 #include <sys/cpc_impl.h>
59 60 #include <sys/uadmin.h>
60 61 #include <sys/panic.h>
61 62 #include <sys/debug.h>
62 63 #include <sys/archsystm.h>
63 64 #include <sys/trap.h>
64 65 #include <sys/machsystm.h>
65 66 #include <sys/cpuvar.h>
66 67 #include <sys/rm_platter.h>
67 68 #include <sys/privregs.h>
68 69 #include <sys/cyclic.h>
69 70 #include <sys/note.h>
70 71 #include <sys/pci_intr_lib.h>
71 72 #include <sys/sunndi.h>
72 73 #if !defined(__xpv)
73 74 #include <sys/hpet.h>
74 75 #include <sys/clock.h>
75 76 #endif
76 77
77 78 /*
78 79 * Local Function Prototypes
79 80 */
80 81 static int apic_handle_defconf();
81 82 static int apic_parse_mpct(caddr_t mpct, int bypass);
82 83 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
83 84 static int apic_checksum(caddr_t bptr, int len);
84 85 static int apic_find_bus_type(char *bus);
85 86 static int apic_find_bus(int busid);
86 87 static struct apic_io_intr *apic_find_io_intr(int irqno);
87 88 static int apic_find_free_irq(int start, int end);
88 89 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
89 90 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
90 91 static void apic_free_apic_cpus(void);
91 92 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
92 93 static int apic_acpi_enter_apicmode(void);
93 94
94 95 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
95 96 int child_ipin, struct apic_io_intr **intrp);
96 97 int apic_find_bus_id(int bustype);
97 98 int apic_find_intin(uchar_t ioapic, uchar_t intin);
98 99 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
99 100
100 101 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
101 102
102 103 /* ACPI SCI interrupt configuration; -1 if SCI not used */
103 104 int apic_sci_vect = -1;
104 105 iflag_t apic_sci_flags;
105 106
106 107 #if !defined(__xpv)
107 108 /* ACPI HPET interrupt configuration; -1 if HPET not used */
108 109 int apic_hpet_vect = -1;
109 110 iflag_t apic_hpet_flags;
110 111 #endif
111 112
112 113 /*
113 114 * psm name pointer
114 115 */
115 116 char *psm_name;
116 117
117 118 /* ACPI support routines */
118 119 static int acpi_probe(char *);
119 120 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
120 121 int *pci_irqp, iflag_t *intr_flagp);
121 122
122 123 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
123 124 int ipin, int *pci_irqp, iflag_t *intr_flagp);
124 125 uchar_t acpi_find_ioapic(int irq);
125 126 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
126 127
127 128 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
128 129 int apic_max_reps_clear_pending = 1000;
129 130
130 131 int apic_intr_policy = INTR_ROUND_ROBIN;
131 132
132 133 int apic_next_bind_cpu = 1; /* For round robin assignment */
133 134 /* start with cpu 1 */
134 135
135 136 /*
136 137 * If enabled, the distribution works as follows:
137 138 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
138 139 * and the irq corresponding to the ipl is also set in the aci_current array.
139 140 * interrupt exit and setspl (due to soft interrupts) will cause the current
140 141 * ipl to be be changed. This is cache friendly as these frequently used
141 142 * paths write into a per cpu structure.
142 143 *
143 144 * Sampling is done by checking the structures for all CPUs and incrementing
144 145 * the busy field of the irq (if any) executing on each CPU and the busy field
145 146 * of the corresponding CPU.
146 147 * In periodic mode this is done on every clock interrupt.
147 148 * In one-shot mode, this is done thru a cyclic with an interval of
148 149 * apic_redistribute_sample_interval (default 10 milli sec).
149 150 *
150 151 * Every apic_sample_factor_redistribution times we sample, we do computations
151 152 * to decide which interrupt needs to be migrated (see comments
152 153 * before apic_intr_redistribute().
153 154 */
154 155
155 156 /*
156 157 * Following 3 variables start as % and can be patched or set using an
157 158 * API to be defined in future. They will be scaled to
158 159 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
159 160 * mode), or 101 in one-shot mode to stagger it away from one sec processing
160 161 */
161 162
162 163 int apic_int_busy_mark = 60;
163 164 int apic_int_free_mark = 20;
164 165 int apic_diff_for_redistribution = 10;
165 166
166 167 /* sampling interval for interrupt redistribution for dynamic migration */
167 168 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
168 169
169 170 /*
170 171 * number of times we sample before deciding to redistribute interrupts
171 172 * for dynamic migration
172 173 */
173 174 int apic_sample_factor_redistribution = 101;
174 175
175 176 int apic_redist_cpu_skip = 0;
176 177 int apic_num_imbalance = 0;
177 178 int apic_num_rebind = 0;
178 179
179 180 /*
180 181 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
181 182 * allocation of CPU ids is disabled.
182 183 */
183 184 int apic_max_nproc = -1;
184 185 int apic_nproc = 0;
185 186 size_t apic_cpus_size = 0;
186 187 int apic_defconf = 0;
187 188 int apic_irq_translate = 0;
188 189 int apic_spec_rev = 0;
189 190 int apic_imcrp = 0;
190 191
191 192 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
192 193 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
193 194
194 195 /*
195 196 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
196 197 * will be assigned (via _SRS). If it is not set, use the current
197 198 * irq setting (via _CRS), but only if that irq is in the set of possible
198 199 * irqs (returned by _PRS) for the device.
199 200 */
200 201 int apic_unconditional_srs = 1;
201 202
202 203 /*
203 204 * For interrupt link devices, if apic_prefer_crs is set when we are
204 205 * assigning an IRQ resource to a device, prefer the current IRQ setting
205 206 * over other possible irq settings under same conditions.
206 207 */
207 208
208 209 int apic_prefer_crs = 1;
209 210
210 211 uchar_t apic_io_id[MAX_IO_APIC];
211 212 volatile uint32_t *apicioadr[MAX_IO_APIC];
212 213 uchar_t apic_io_ver[MAX_IO_APIC];
213 214 uchar_t apic_io_vectbase[MAX_IO_APIC];
214 215 uchar_t apic_io_vectend[MAX_IO_APIC];
215 216 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
216 217 uint32_t apic_physaddr[MAX_IO_APIC];
217 218
218 219 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
219 220
220 221 /*
221 222 * First available slot to be used as IRQ index into the apic_irq_table
222 223 * for those interrupts (like MSI/X) that don't have a physical IRQ.
223 224 */
224 225 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
225 226
226 227 /*
227 228 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
228 229 * and bound elements of cpus_info and the temp_cpu element of irq_struct
229 230 */
230 231 lock_t apic_ioapic_lock;
231 232
232 233 int apic_io_max = 0; /* no. of i/o apics enabled */
233 234
234 235 struct apic_io_intr *apic_io_intrp = NULL;
235 236 static struct apic_bus *apic_busp;
236 237
237 238 uchar_t apic_resv_vector[MAXIPL+1];
238 239
239 240 char apic_level_intr[APIC_MAX_VECTOR+1];
240 241
241 242 uint32_t eisa_level_intr_mask = 0;
242 243 /* At least MSB will be set if EISA bus */
243 244
244 245 int apic_pci_bus_total = 0;
245 246 uchar_t apic_single_pci_busid = 0;
246 247
247 248 /*
248 249 * airq_mutex protects additions to the apic_irq_table - the first
249 250 * pointer and any airq_nexts off of that one. It also protects
250 251 * apic_max_device_irq & apic_min_device_irq. It also guarantees
251 252 * that share_id is unique as new ids are generated only when new
252 253 * irq_t structs are linked in. Once linked in the structs are never
253 254 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
254 255 * or allocated. Note that there is a slight gap between allocating in
255 256 * apic_introp_xlate and programming in addspl.
256 257 */
257 258 kmutex_t airq_mutex;
258 259 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
259 260 int apic_max_device_irq = 0;
260 261 int apic_min_device_irq = APIC_MAX_VECTOR;
261 262
262 263 typedef struct prs_irq_list_ent {
263 264 int list_prio;
264 265 int32_t irq;
265 266 iflag_t intrflags;
266 267 acpi_prs_private_t prsprv;
267 268 struct prs_irq_list_ent *next;
268 269 } prs_irq_list_t;
269 270
270 271
271 272 /*
272 273 * ACPI variables
273 274 */
274 275 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
275 276 int apic_enable_acpi = 0;
276 277
277 278 /* ACPI Multiple APIC Description Table ptr */
278 279 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
279 280
280 281 /* ACPI Interrupt Source Override Structure ptr */
281 282 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
282 283 int acpi_iso_cnt = 0;
283 284
284 285 /* ACPI Non-maskable Interrupt Sources ptr */
285 286 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
286 287 static int acpi_nmi_scnt = 0;
287 288 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
288 289 static int acpi_nmi_ccnt = 0;
289 290
290 291 static boolean_t acpi_found_smp_config = B_FALSE;
291 292
292 293 /*
293 294 * The following added to identify a software poweroff method if available.
294 295 */
295 296
296 297 static struct {
297 298 int poweroff_method;
298 299 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
299 300 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
300 301 } apic_mps_ids[] = {
301 302 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
302 303 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
303 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
304 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
305 306 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
306 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
307 308 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
308 309 };
309 310
310 311 int apic_poweroff_method = APIC_POWEROFF_NONE;
311 312
312 313 /*
313 314 * Auto-configuration routines
314 315 */
315 316
316 317 /*
317 318 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
318 319 * May work with 1.1 - but not guaranteed.
319 320 * According to the MP Spec, the MP floating pointer structure
320 321 * will be searched in the order described below:
321 322 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
322 323 * 2. Within the last kilobyte of system base memory
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323 324 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
324 325 * Once we find the right signature with proper checksum, we call
325 326 * either handle_defconf or parse_mpct to get all info necessary for
326 327 * subsequent operations.
327 328 */
328 329 int
329 330 apic_probe_common(char *modname)
330 331 {
331 332 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
332 333 caddr_t biosdatap;
333 - caddr_t mpct = 0;
334 + caddr_t mpct = NULL;
334 335 caddr_t fptr;
335 - int i, mpct_size, mapsize, retval = PSM_FAILURE;
336 + int i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
336 337 ushort_t ebda_seg, base_mem_size;
337 338 struct apic_mpfps_hdr *fpsp;
338 339 struct apic_mp_cnf_hdr *hdrp;
339 340 int bypass_cpu_and_ioapics_in_mptables;
340 341 int acpi_user_options;
341 342
342 343 if (apic_forceload < 0)
343 344 return (retval);
344 345
345 346 /*
346 347 * Remember who we are
347 348 */
348 349 psm_name = modname;
349 350
350 351 /* Allow override for MADT-only mode */
351 352 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
352 353 "acpi-user-options", 0);
353 354 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
354 355
355 356 /* Allow apic_use_acpi to override MADT-only mode */
356 357 if (!apic_use_acpi)
357 358 apic_use_acpi_madt_only = 0;
358 359
359 360 retval = acpi_probe(modname);
360 361
361 362 /* in UEFI system, there is no BIOS data */
362 363 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab"))
363 364 goto apic_ret;
364 365
365 366 /*
366 367 * mapin the bios data area 40:0
367 368 * 40:13h - two-byte location reports the base memory size
368 369 * 40:0Eh - two-byte location for the exact starting address of
369 370 * the EBDA segment for EISA
370 371 */
371 372 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
372 373 if (!biosdatap)
373 374 goto apic_ret;
374 375 fpsp = (struct apic_mpfps_hdr *)NULL;
375 376 mapsize = MPFPS_RAM_WIN_LEN;
376 377 /*LINTED: pointer cast may result in improper alignment */
377 378 ebda_seg = *((ushort_t *)(biosdatap+0xe));
378 379 /* check the 1k of EBDA */
379 380 if (ebda_seg) {
380 381 ebda_start = ((uint32_t)ebda_seg) << 4;
381 382 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
382 383 if (fptr) {
383 384 if (!(fpsp =
384 385 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
385 386 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
386 387 }
387 388 }
388 389 /* If not in EBDA, check the last k of system base memory */
389 390 if (!fpsp) {
390 391 /*LINTED: pointer cast may result in improper alignment */
391 392 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
392 393
393 394 if (base_mem_size > 512)
394 395 base_mem_end = 639 * 1024;
395 396 else
396 397 base_mem_end = 511 * 1024;
397 398 /* if ebda == last k of base mem, skip to check BIOS ROM */
398 399 if (base_mem_end != ebda_start) {
399 400
400 401 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
401 402 PROT_READ);
402 403
403 404 if (fptr) {
404 405 if (!(fpsp = apic_find_fps_sig(fptr,
405 406 MPFPS_RAM_WIN_LEN)))
406 407 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
407 408 }
408 409 }
409 410 }
410 411 psm_unmap_phys(biosdatap, 0x20);
411 412
412 413 /* If still cannot find it, check the BIOS ROM space */
413 414 if (!fpsp) {
414 415 mapsize = MPFPS_ROM_WIN_LEN;
415 416 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
416 417 MPFPS_ROM_WIN_LEN, PROT_READ);
417 418 if (fptr) {
418 419 if (!(fpsp =
419 420 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
420 421 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
421 422 goto apic_ret;
422 423 }
423 424 }
424 425 }
425 426
426 427 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
427 428 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
428 429 goto apic_ret;
429 430 }
430 431
431 432 apic_spec_rev = fpsp->mpfps_spec_rev;
432 433 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
433 434 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
434 435 goto apic_ret;
435 436 }
436 437
437 438 /* check IMCR is present or not */
438 439 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
439 440
440 441 /* check default configuration (dual CPUs) */
441 442 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
442 443 psm_unmap_phys(fptr, mapsize);
443 444 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
444 445 return (retval);
445 446
446 447 goto apic_ret;
447 448 }
448 449
449 450 /* MP Configuration Table */
450 451 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
451 452
452 453 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
453 454
454 455 /*
455 456 * Map in enough memory for the MP Configuration Table Header.
456 457 * Use this table to read the total length of the BIOS data and
457 458 * map in all the info
458 459 */
459 460 /*LINTED: pointer cast may result in improper alignment */
460 461 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
461 462 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
462 463 if (!hdrp)
463 464 goto apic_ret;
464 465
465 466 /* check mp configuration table signature PCMP */
466 467 if (hdrp->mpcnf_sig != 0x504d4350) {
467 468 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
468 469 goto apic_ret;
469 470 }
470 471 mpct_size = (int)hdrp->mpcnf_tbl_length;
471 472
472 473 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
473 474
474 475 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
475 476
476 477 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
477 478 /* This is an ACPI machine No need for further checks */
478 479 goto apic_ret;
479 480 }
480 481
481 482 /*
482 483 * Map in the entries for this machine, ie. Processor
483 484 * Entry Tables, Bus Entry Tables, etc.
484 485 * They are in fixed order following one another
485 486 */
486 487 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
487 488 if (!mpct)
488 489 goto apic_ret;
489 490
490 491 if (apic_checksum(mpct, mpct_size) != 0)
491 492 goto apic_fail1;
492 493
493 494 /*LINTED: pointer cast may result in improper alignment */
494 495 hdrp = (struct apic_mp_cnf_hdr *)mpct;
495 496 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
496 497 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
497 498 if (!apicadr)
498 499 goto apic_fail1;
499 500
500 501 /* Parse all information in the tables */
501 502 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
502 503 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
503 504 PSM_SUCCESS) {
504 505 retval = PSM_SUCCESS;
505 506 goto apic_ret;
506 507 }
507 508
508 509 apic_fail1:
509 510 psm_unmap_phys(mpct, mpct_size);
510 511 mpct = NULL;
511 512
512 513 apic_ret:
513 514 if (retval == PSM_SUCCESS) {
514 515 extern int apic_ioapic_method_probe();
515 516
516 517 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
517 518 return (PSM_SUCCESS);
518 519 }
519 520
520 521 for (i = 0; i < apic_io_max; i++)
521 522 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
522 523 if (apic_cpus) {
523 524 kmem_free(apic_cpus, apic_cpus_size);
524 525 apic_cpus = NULL;
525 526 }
526 527 if (apicadr) {
527 528 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
528 529 apicadr = NULL;
529 530 }
530 531 if (mpct)
531 532 psm_unmap_phys(mpct, mpct_size);
532 533
533 534 return (retval);
534 535 }
535 536
536 537 static void
537 538 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
538 539 {
539 540 int i;
540 541
541 542 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
542 543 i++) {
543 544 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
544 545 strlen(apic_mps_ids[i].oem_id)) == 0) &&
545 546 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
546 547 strlen(apic_mps_ids[i].prod_id)) == 0)) {
547 548
548 549 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
549 550 break;
550 551 }
551 552 }
552 553
553 554 if (apic_debug_mps_id != 0) {
554 555 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
555 556 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
556 557 psm_name,
557 558 hdrp->mpcnf_oem_str[0],
558 559 hdrp->mpcnf_oem_str[1],
559 560 hdrp->mpcnf_oem_str[2],
560 561 hdrp->mpcnf_oem_str[3],
561 562 hdrp->mpcnf_oem_str[4],
562 563 hdrp->mpcnf_oem_str[5],
563 564 hdrp->mpcnf_oem_str[6],
564 565 hdrp->mpcnf_oem_str[7],
565 566 hdrp->mpcnf_prod_str[0],
566 567 hdrp->mpcnf_prod_str[1],
567 568 hdrp->mpcnf_prod_str[2],
568 569 hdrp->mpcnf_prod_str[3],
569 570 hdrp->mpcnf_prod_str[4],
570 571 hdrp->mpcnf_prod_str[5],
571 572 hdrp->mpcnf_prod_str[6],
572 573 hdrp->mpcnf_prod_str[7],
573 574 hdrp->mpcnf_prod_str[8],
574 575 hdrp->mpcnf_prod_str[9],
575 576 hdrp->mpcnf_prod_str[10],
576 577 hdrp->mpcnf_prod_str[11]);
577 578 }
578 579 }
579 580
580 581 static void
581 582 apic_free_apic_cpus(void)
582 583 {
583 584 if (apic_cpus != NULL) {
584 585 kmem_free(apic_cpus, apic_cpus_size);
585 586 apic_cpus = NULL;
586 587 apic_cpus_size = 0;
587 588 }
588 589 }
589 590
590 591 static int
591 592 acpi_probe(char *modname)
592 593 {
593 594 int i, intmax, index;
594 595 uint32_t id, ver;
595 596 int acpi_verboseflags = 0;
596 597 int madt_seen, madt_size;
597 598 ACPI_SUBTABLE_HEADER *ap;
598 599 ACPI_MADT_LOCAL_APIC *mpa;
599 600 ACPI_MADT_LOCAL_X2APIC *mpx2a;
600 601 ACPI_MADT_IO_APIC *mia;
601 602 ACPI_MADT_IO_SAPIC *misa;
602 603 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
603 604 ACPI_MADT_NMI_SOURCE *mns;
604 605 ACPI_MADT_INTERRUPT_SOURCE *mis;
605 606 ACPI_MADT_LOCAL_APIC_NMI *mlan;
606 607 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
607 608 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
608 609 int sci;
609 610 iflag_t sci_flags;
610 611 volatile uint32_t *ioapic;
611 612 int ioapic_ix;
612 613 uint32_t *local_ids;
613 614 uint32_t *proc_ids;
614 615 uchar_t hid;
615 616 int warned = 0;
616 617
617 618 if (!apic_use_acpi)
618 619 return (PSM_FAILURE);
619 620
620 621 if (AcpiGetTable(ACPI_SIG_MADT, 1,
621 622 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
622 623 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
623 624 return (PSM_FAILURE);
624 625 }
625 626
626 627 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
627 628 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
628 629 if (!apicadr)
629 630 return (PSM_FAILURE);
630 631
631 632 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
632 633 KM_NOSLEEP)) == NULL)
633 634 return (PSM_FAILURE);
634 635
635 636 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
636 637 KM_NOSLEEP)) == NULL) {
637 638 kmem_free(local_ids, NCPU * sizeof (uint32_t));
638 639 return (PSM_FAILURE);
639 640 }
640 641
641 642 id = apic_reg_ops->apic_read(APIC_LID_REG);
642 643 local_ids[0] = (uchar_t)(id >> 24);
643 644 apic_nproc = index = 1;
644 645 apic_io_max = 0;
645 646
646 647 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
647 648 madt_size = acpi_mapic_dtp->Header.Length;
648 649 madt_seen = sizeof (*acpi_mapic_dtp);
649 650
650 651 while (madt_seen < madt_size) {
651 652 switch (ap->Type) {
652 653 case ACPI_MADT_TYPE_LOCAL_APIC:
653 654 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
654 655 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
655 656 if (mpa->Id == 255) {
656 657 cmn_err(CE_WARN, "!%s: encountered "
657 658 "invalid entry in MADT: CPU %d "
658 659 "has Local APIC Id equal to 255 ",
659 660 psm_name, mpa->ProcessorId);
660 661 }
661 662 if (mpa->Id == local_ids[0]) {
662 663 ASSERT(index == 1);
663 664 proc_ids[0] = mpa->ProcessorId;
664 665 } else if (apic_nproc < NCPU && use_mp &&
665 666 apic_nproc < boot_ncpus) {
666 667 local_ids[index] = mpa->Id;
667 668 proc_ids[index] = mpa->ProcessorId;
668 669 index++;
669 670 apic_nproc++;
670 671 } else if (apic_nproc == NCPU && !warned) {
671 672 cmn_err(CE_WARN, "%s: CPU limit "
672 673 "exceeded"
673 674 #if !defined(__amd64)
674 675 " for 32-bit mode"
675 676 #endif
676 677 "; Solaris will use %d CPUs.",
677 678 psm_name, NCPU);
678 679 warned = 1;
679 680 }
680 681 }
681 682 break;
682 683
683 684 case ACPI_MADT_TYPE_IO_APIC:
684 685 mia = (ACPI_MADT_IO_APIC *) ap;
685 686 if (apic_io_max < MAX_IO_APIC) {
686 687 ioapic_ix = apic_io_max;
687 688 apic_io_id[apic_io_max] = mia->Id;
688 689 apic_io_vectbase[apic_io_max] =
689 690 mia->GlobalIrqBase;
690 691 apic_physaddr[apic_io_max] =
691 692 (uint32_t)mia->Address;
692 693 ioapic = apicioadr[apic_io_max] =
693 694 mapin_ioapic((uint32_t)mia->Address,
694 695 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
695 696 if (!ioapic)
696 697 goto cleanup;
697 698 ioapic_mask_workaround[apic_io_max] =
698 699 apic_is_ioapic_AMD_813x(mia->Address);
699 700 apic_io_max++;
700 701 }
701 702 break;
702 703
703 704 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
704 705 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
705 706 if (acpi_isop == NULL)
706 707 acpi_isop = mio;
707 708 acpi_iso_cnt++;
708 709 break;
709 710
710 711 case ACPI_MADT_TYPE_NMI_SOURCE:
711 712 /* UNIMPLEMENTED */
712 713 mns = (ACPI_MADT_NMI_SOURCE *) ap;
713 714 if (acpi_nmi_sp == NULL)
714 715 acpi_nmi_sp = mns;
715 716 acpi_nmi_scnt++;
716 717
717 718 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
718 719 mns->GlobalIrq, mns->IntiFlags);
719 720 break;
720 721
721 722 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
722 723 /* UNIMPLEMENTED */
723 724 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
724 725 if (acpi_nmi_cp == NULL)
725 726 acpi_nmi_cp = mlan;
726 727 acpi_nmi_ccnt++;
727 728
728 729 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
729 730 mlan->ProcessorId, mlan->IntiFlags,
730 731 mlan->Lint);
731 732 break;
732 733
733 734 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
734 735 /* UNIMPLEMENTED */
735 736 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
736 737 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
737 738 (long)mao->Address);
738 739 break;
739 740
740 741 case ACPI_MADT_TYPE_IO_SAPIC:
741 742 /* UNIMPLEMENTED */
742 743 misa = (ACPI_MADT_IO_SAPIC *) ap;
743 744
744 745 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
745 746 misa->Id, misa->GlobalIrqBase,
746 747 (long)misa->Address);
747 748 break;
748 749
749 750 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
750 751 /* UNIMPLEMENTED */
751 752 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
752 753
753 754 cmn_err(CE_NOTE,
754 755 "!apic: irq source: %d %d %d 0x%x %d %d\n",
755 756 mis->Id, mis->Eid, mis->GlobalIrq,
756 757 mis->IntiFlags, mis->Type,
757 758 mis->IoSapicVector);
758 759 break;
759 760
760 761 case ACPI_MADT_TYPE_LOCAL_X2APIC:
761 762 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
762 763
763 764 /*
764 765 * All logical processors with APIC ID values
765 766 * of 255 and greater will have their APIC
766 767 * reported through Processor X2APIC structure.
767 768 * All logical processors with APIC ID less than
768 769 * 255 will have their APIC reported through
769 770 * Processor Local APIC.
770 771 *
771 772 * Some systems apparently don't care and report all
772 773 * processors through Processor X2APIC structures. We
773 774 * warn about that but don't ignore those CPUs.
774 775 */
775 776 if (mpx2a->LocalApicId < 255) {
776 777 cmn_err(CE_WARN, "!%s: ignoring invalid entry "
777 778 "in MADT: CPU %d has X2APIC Id %d (< 255)",
778 779 psm_name, mpx2a->Uid, mpx2a->LocalApicId);
779 780 }
780 781 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
781 782 if (mpx2a->LocalApicId == local_ids[0]) {
782 783 ASSERT(index == 1);
783 784 proc_ids[0] = mpx2a->Uid;
784 785 } else if (apic_nproc < NCPU && use_mp &&
785 786 apic_nproc < boot_ncpus) {
786 787 local_ids[index] = mpx2a->LocalApicId;
787 788 proc_ids[index] = mpx2a->Uid;
788 789 index++;
789 790 apic_nproc++;
790 791 } else if (apic_nproc == NCPU && !warned) {
791 792 cmn_err(CE_WARN, "%s: CPU limit "
792 793 "exceeded"
793 794 #if !defined(__amd64)
794 795 " for 32-bit mode"
795 796 #endif
796 797 "; Solaris will use %d CPUs.",
797 798 psm_name, NCPU);
798 799 warned = 1;
799 800 }
800 801 }
801 802
802 803 break;
803 804
804 805 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
805 806 /* UNIMPLEMENTED */
806 807 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
807 808 if (mx2alan->Uid >> 8)
808 809 acpi_nmi_ccnt++;
809 810
810 811 #ifdef DEBUG
811 812 cmn_err(CE_NOTE,
812 813 "!apic: local x2apic nmi: %d 0x%x %d\n",
813 814 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
814 815 #endif
815 816
816 817 break;
817 818
818 819 case ACPI_MADT_TYPE_RESERVED:
819 820 default:
820 821 break;
821 822 }
822 823
823 824 /* advance to next entry */
824 825 madt_seen += ap->Length;
825 826 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
826 827 }
827 828
828 829 /* We found multiple enabled cpus via MADT */
829 830 if ((apic_nproc > 1) && (apic_io_max > 0)) {
830 831 acpi_found_smp_config = B_TRUE;
831 832 cmn_err(CE_NOTE,
832 833 "!apic: Using ACPI (MADT) for SMP configuration");
833 834 }
834 835
835 836 /*
836 837 * allocate enough space for possible hot-adding of CPUs.
837 838 * max_ncpus may be less than apic_nproc if it's set by user.
838 839 */
839 840 if (plat_dr_support_cpu()) {
840 841 apic_max_nproc = max_ncpus;
841 842 }
842 843 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
843 844 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
844 845 goto cleanup;
845 846
846 847 /*
847 848 * ACPI doesn't provide the local apic ver, get it directly from the
848 849 * local apic
849 850 */
850 851 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
851 852 for (i = 0; i < apic_nproc; i++) {
852 853 apic_cpus[i].aci_local_id = local_ids[i];
853 854 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
854 855 apic_cpus[i].aci_processor_id = proc_ids[i];
855 856 /* Only build mapping info for CPUs present at boot. */
856 857 if (i < boot_ncpus)
857 858 (void) acpica_map_cpu(i, proc_ids[i]);
858 859 }
859 860
860 861 /*
861 862 * To support CPU dynamic reconfiguration, the apic CPU info structure
862 863 * for each possible CPU will be pre-allocated at boot time.
863 864 * The state for each apic CPU info structure will be assigned according
864 865 * to the following rules:
865 866 * Rule 1:
866 867 * Slot index range: [0, min(apic_nproc, boot_ncpus))
867 868 * State flags: 0
868 869 * Note: cpu exists and will be configured/enabled at boot time
869 870 * Rule 2:
870 871 * Slot index range: [boot_ncpus, apic_nproc)
871 872 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
872 873 * Note: cpu exists but won't be configured/enabled at boot time
873 874 * Rule 3:
874 875 * Slot index range: [apic_nproc, boot_ncpus)
875 876 * State flags: APIC_CPU_FREE
876 877 * Note: cpu doesn't exist at boot time
877 878 * Rule 4:
878 879 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
879 880 * State flags: APIC_CPU_FREE
880 881 * Note: cpu doesn't exist at boot time
881 882 */
882 883 CPUSET_ZERO(apic_cpumask);
883 884 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
884 885 CPUSET_ADD(apic_cpumask, i);
885 886 apic_cpus[i].aci_status = 0;
886 887 }
887 888 for (i = boot_ncpus; i < apic_nproc; i++) {
888 889 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
889 890 }
890 891 for (i = apic_nproc; i < boot_ncpus; i++) {
891 892 apic_cpus[i].aci_status = APIC_CPU_FREE;
892 893 }
893 894 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
894 895 apic_cpus[i].aci_status = APIC_CPU_FREE;
895 896 }
896 897
897 898 for (i = 0; i < apic_io_max; i++) {
898 899 ioapic_ix = i;
899 900
900 901 /*
901 902 * need to check Sitka on the following acpi problem
902 903 * On the Sitka, the ioapic's apic_id field isn't reporting
903 904 * the actual io apic id. We have reported this problem
904 905 * to Intel. Until they fix the problem, we will get the
905 906 * actual id directly from the ioapic.
906 907 */
907 908 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
908 909 hid = (uchar_t)(id >> 24);
909 910
910 911 if (hid != apic_io_id[i]) {
911 912 if (apic_io_id[i] == 0)
912 913 apic_io_id[i] = hid;
913 914 else { /* set ioapic id to whatever reported by ACPI */
914 915 id = ((uint32_t)apic_io_id[i]) << 24;
915 916 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
916 917 }
917 918 }
918 919 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
919 920 apic_io_ver[i] = (uchar_t)(ver & 0xff);
920 921 intmax = (ver >> 16) & 0xff;
921 922 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
922 923 if (apic_first_avail_irq <= apic_io_vectend[i])
923 924 apic_first_avail_irq = apic_io_vectend[i] + 1;
924 925 }
925 926
926 927
927 928 /*
928 929 * Process SCI configuration here
929 930 * An error may be returned here if
930 931 * acpi-user-options specifies legacy mode
931 932 * (no SCI, no ACPI mode)
932 933 */
933 934 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
934 935 sci = -1;
935 936
936 937 /*
937 938 * Now call acpi_init() to generate namespaces
938 939 * If this fails, we don't attempt to use ACPI
939 940 * even if we were able to get a MADT above
940 941 */
941 942 if (acpica_init() != AE_OK) {
942 943 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
943 944 goto cleanup;
944 945 }
945 946
946 947 /*
947 948 * Call acpica_build_processor_map() now that we have
948 949 * ACPI namesspace access
949 950 */
950 951 (void) acpica_build_processor_map();
951 952
952 953 /*
953 954 * Squirrel away the SCI and flags for later on
954 955 * in apic_picinit() when we're ready
955 956 */
956 957 apic_sci_vect = sci;
957 958 apic_sci_flags = sci_flags;
958 959
959 960 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
960 961 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
961 962
962 963 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
963 964 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
964 965
965 966 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
966 967 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
967 968
968 969 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
969 970 goto cleanup;
970 971
971 972 /* Enable ACPI APIC interrupt routing */
972 973 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
973 974 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
974 975 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
975 976 apic_enable_acpi = 1;
976 977 if (apic_sci_vect > 0) {
977 978 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
978 979 }
979 980 if (apic_use_acpi_madt_only) {
980 981 cmn_err(CE_CONT,
981 982 "?Using ACPI for CPU/IOAPIC information ONLY\n");
982 983 }
983 984
984 985 #if !defined(__xpv)
985 986 /*
986 987 * probe ACPI for hpet information here which is used later
987 988 * in apic_picinit().
988 989 */
989 990 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
990 991 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
991 992 }
992 993 #endif
993 994
994 995 kmem_free(local_ids, NCPU * sizeof (uint32_t));
995 996 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
996 997 return (PSM_SUCCESS);
997 998 }
998 999 /* if setting APIC mode failed above, we fall through to cleanup */
999 1000
1000 1001 cleanup:
1001 1002 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
1002 1003 acpi_found_smp_config ? "found" : "not found");
1003 1004 apic_free_apic_cpus();
1004 1005 if (apicadr != NULL) {
1005 1006 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1006 1007 apicadr = NULL;
1007 1008 }
1008 1009 apic_max_nproc = -1;
1009 1010 apic_nproc = 0;
1010 1011 for (i = 0; i < apic_io_max; i++) {
1011 1012 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
1012 1013 apicioadr[i] = NULL;
1013 1014 }
1014 1015 apic_io_max = 0;
1015 1016 acpi_isop = NULL;
1016 1017 acpi_iso_cnt = 0;
1017 1018 acpi_nmi_sp = NULL;
1018 1019 acpi_nmi_scnt = 0;
1019 1020 acpi_nmi_cp = NULL;
1020 1021 acpi_nmi_ccnt = 0;
1021 1022 acpi_found_smp_config = B_FALSE;
1022 1023 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1023 1024 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1024 1025 return (PSM_FAILURE);
1025 1026 }
1026 1027
1027 1028 /*
1028 1029 * Handle default configuration. Fill in reqd global variables & tables
1029 1030 * Fill all details as MP table does not give any more info
1030 1031 */
1031 1032 static int
1032 1033 apic_handle_defconf()
1033 1034 {
1034 1035 uint_t lid;
1035 1036
1036 1037 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1037 1038 apic_max_nproc = -1;
1038 1039 apic_free_apic_cpus();
1039 1040 plat_dr_disable_cpu();
1040 1041
1041 1042 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1042 1043 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1043 1044 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1044 1045 APIC_LOCAL_MEMLEN, PROT_READ);
1045 1046 apic_cpus_size = 2 * sizeof (*apic_cpus);
1046 1047 apic_cpus = (apic_cpus_info_t *)
1047 1048 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1048 1049 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1049 1050 goto apic_handle_defconf_fail;
1050 1051 CPUSET_ONLY(apic_cpumask, 0);
1051 1052 CPUSET_ADD(apic_cpumask, 1);
1052 1053 apic_nproc = 2;
1053 1054 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1054 1055 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1055 1056 /*
1056 1057 * According to the PC+MP spec 1.1, the local ids
1057 1058 * for the default configuration has to be 0 or 1
1058 1059 */
1059 1060 if (apic_cpus[0].aci_local_id == 1)
1060 1061 apic_cpus[1].aci_local_id = 0;
1061 1062 else if (apic_cpus[0].aci_local_id == 0)
1062 1063 apic_cpus[1].aci_local_id = 1;
1063 1064 else
1064 1065 goto apic_handle_defconf_fail;
1065 1066
1066 1067 apic_io_id[0] = 2;
1067 1068 apic_io_max = 1;
1068 1069 if (apic_defconf >= 5) {
1069 1070 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1070 1071 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1071 1072 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1072 1073 } else {
1073 1074 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1074 1075 apic_cpus[1].aci_local_ver = 0;
1075 1076 apic_io_ver[0] = 0;
1076 1077 }
1077 1078 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1078 1079 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1079 1080 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1080 1081 return (PSM_SUCCESS);
1081 1082
1082 1083 apic_handle_defconf_fail:
1083 1084 if (apicadr)
1084 1085 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1085 1086 if (apicioadr[0])
1086 1087 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1087 1088 return (PSM_FAILURE);
1088 1089 }
1089 1090
1090 1091 /* Parse the entries in MP configuration table and collect info that we need */
1091 1092 static int
1092 1093 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1093 1094 {
1094 1095 struct apic_procent *procp;
1095 1096 struct apic_bus *busp;
1096 1097 struct apic_io_entry *ioapicp;
1097 1098 struct apic_io_intr *intrp;
1098 1099 int ioapic_ix;
1099 1100 uint_t lid;
1100 1101 uint32_t id;
1101 1102 uchar_t hid;
1102 1103 int warned = 0;
1103 1104
1104 1105 /*LINTED: pointer cast may result in improper alignment */
1105 1106 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1106 1107
1107 1108 /* No need to count cpu entries if we won't use them */
1108 1109 if (!bypass_cpus_and_ioapics) {
1109 1110
1110 1111 /* Find max # of CPUS and allocate structure accordingly */
1111 1112 apic_nproc = 0;
1112 1113 CPUSET_ZERO(apic_cpumask);
1113 1114 while (procp->proc_entry == APIC_CPU_ENTRY) {
1114 1115 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1115 1116 if (apic_nproc < NCPU && use_mp &&
1116 1117 apic_nproc < boot_ncpus) {
1117 1118 CPUSET_ADD(apic_cpumask, apic_nproc);
1118 1119 apic_nproc++;
1119 1120 } else if (apic_nproc == NCPU && !warned) {
1120 1121 cmn_err(CE_WARN, "%s: CPU limit "
1121 1122 "exceeded"
1122 1123 #if !defined(__amd64)
1123 1124 " for 32-bit mode"
1124 1125 #endif
1125 1126 "; Solaris will use %d CPUs.",
1126 1127 psm_name, NCPU);
1127 1128 warned = 1;
1128 1129 }
1129 1130
1130 1131 }
1131 1132 procp++;
1132 1133 }
1133 1134 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1134 1135 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1135 1136 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1136 1137 return (PSM_FAILURE);
1137 1138 }
1138 1139
1139 1140 /*LINTED: pointer cast may result in improper alignment */
1140 1141 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1141 1142
1142 1143 /*
1143 1144 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1144 1145 * if we're bypassing this information, it has already been filled
1145 1146 * in by acpi_probe(), so don't overwrite it.
1146 1147 */
1147 1148 if (!bypass_cpus_and_ioapics)
1148 1149 apic_nproc = 1;
1149 1150
1150 1151 while (procp->proc_entry == APIC_CPU_ENTRY) {
1151 1152 /* check whether the cpu exists or not */
1152 1153 if (!bypass_cpus_and_ioapics &&
1153 1154 procp->proc_cpuflags & CPUFLAGS_EN) {
1154 1155 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1155 1156 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1156 1157 apic_cpus[0].aci_local_id = procp->proc_apicid;
1157 1158 if (apic_cpus[0].aci_local_id !=
1158 1159 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1159 1160 return (PSM_FAILURE);
1160 1161 }
1161 1162 apic_cpus[0].aci_local_ver =
1162 1163 procp->proc_version;
1163 1164 } else if (apic_nproc < NCPU && use_mp &&
1164 1165 apic_nproc < boot_ncpus) {
1165 1166 apic_cpus[apic_nproc].aci_local_id =
1166 1167 procp->proc_apicid;
1167 1168
1168 1169 apic_cpus[apic_nproc].aci_local_ver =
1169 1170 procp->proc_version;
1170 1171 apic_nproc++;
1171 1172
1172 1173 }
1173 1174 }
1174 1175 procp++;
1175 1176 }
1176 1177
1177 1178 /*
1178 1179 * Save start of bus entries for later use.
1179 1180 * Get EISA level cntrl if EISA bus is present.
1180 1181 * Also get the CPI bus id for single CPI bus case
1181 1182 */
1182 1183 apic_busp = busp = (struct apic_bus *)procp;
1183 1184 while (busp->bus_entry == APIC_BUS_ENTRY) {
1184 1185 lid = apic_find_bus_type((char *)&busp->bus_str1);
1185 1186 if (lid == BUS_EISA) {
1186 1187 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1187 1188 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1188 1189 } else if (lid == BUS_PCI) {
1189 1190 /*
1190 1191 * apic_single_pci_busid will be used only if
1191 1192 * apic_pic_bus_total is equal to 1
1192 1193 */
1193 1194 apic_pci_bus_total++;
1194 1195 apic_single_pci_busid = busp->bus_id;
1195 1196 }
1196 1197 busp++;
1197 1198 }
1198 1199
1199 1200 ioapicp = (struct apic_io_entry *)busp;
1200 1201
1201 1202 if (!bypass_cpus_and_ioapics)
1202 1203 apic_io_max = 0;
1203 1204 do {
1204 1205 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1205 1206 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1206 1207 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1207 1208 apic_io_ver[apic_io_max] = ioapicp->io_version;
1208 1209 apicioadr[apic_io_max] =
1209 1210 (void *)mapin_ioapic(
1210 1211 (uint32_t)ioapicp->io_apic_addr,
1211 1212 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1212 1213
1213 1214 if (!apicioadr[apic_io_max])
1214 1215 return (PSM_FAILURE);
1215 1216
1216 1217 ioapic_mask_workaround[apic_io_max] =
1217 1218 apic_is_ioapic_AMD_813x(
1218 1219 ioapicp->io_apic_addr);
1219 1220
1220 1221 ioapic_ix = apic_io_max;
1221 1222 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1222 1223 hid = (uchar_t)(id >> 24);
1223 1224
1224 1225 if (hid != apic_io_id[apic_io_max]) {
1225 1226 if (apic_io_id[apic_io_max] == 0)
1226 1227 apic_io_id[apic_io_max] = hid;
1227 1228 else {
1228 1229 /*
1229 1230 * set ioapic id to whatever
1230 1231 * reported by MPS
1231 1232 *
1232 1233 * may not need to set index
1233 1234 * again ???
1234 1235 * take it out and try
1235 1236 */
1236 1237
1237 1238 id = ((uint32_t)
1238 1239 apic_io_id[apic_io_max]) <<
1239 1240 24;
1240 1241
1241 1242 ioapic_write(ioapic_ix,
1242 1243 APIC_ID_CMD, id);
1243 1244 }
1244 1245 }
1245 1246 apic_io_max++;
1246 1247 }
1247 1248 }
1248 1249 ioapicp++;
1249 1250 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1250 1251
1251 1252 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1252 1253
1253 1254 intrp = apic_io_intrp;
1254 1255 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1255 1256 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1256 1257 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1257 1258 apic_irq_translate = 1;
1258 1259 break;
1259 1260 }
1260 1261 intrp++;
1261 1262 }
1262 1263
1263 1264 return (PSM_SUCCESS);
1264 1265 }
1265 1266
1266 1267 boolean_t
1267 1268 apic_cpu_in_range(int cpu)
1268 1269 {
1269 1270 cpu &= ~IRQ_USER_BOUND;
1270 1271 /* Check whether cpu id is in valid range. */
1271 1272 if (cpu < 0 || cpu >= apic_nproc) {
1272 1273 return (B_FALSE);
1273 1274 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1274 1275 /*
1275 1276 * Check whether cpuid is in valid range if CPU DR is enabled.
1276 1277 */
1277 1278 return (B_FALSE);
1278 1279 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1279 1280 return (B_FALSE);
1280 1281 }
1281 1282
1282 1283 return (B_TRUE);
1283 1284 }
1284 1285
1285 1286 processorid_t
1286 1287 apic_get_next_bind_cpu(void)
1287 1288 {
1288 1289 int i, count;
1289 1290 processorid_t cpuid = 0;
1290 1291
1291 1292 for (count = 0; count < apic_nproc; count++) {
1292 1293 if (apic_next_bind_cpu >= apic_nproc) {
1293 1294 apic_next_bind_cpu = 0;
1294 1295 }
1295 1296 i = apic_next_bind_cpu++;
1296 1297 if (apic_cpu_in_range(i)) {
1297 1298 cpuid = i;
1298 1299 break;
1299 1300 }
1300 1301 }
1301 1302
1302 1303 return (cpuid);
1303 1304 }
1304 1305
1305 1306 uint16_t
1306 1307 apic_get_apic_version()
1307 1308 {
1308 1309 int i;
1309 1310 uchar_t min_io_apic_ver = 0;
1310 1311 static uint16_t version; /* Cache as value is constant */
1311 1312 static boolean_t found = B_FALSE; /* Accomodate zero version */
1312 1313
1313 1314 if (found == B_FALSE) {
1314 1315 found = B_TRUE;
1315 1316
1316 1317 /*
1317 1318 * Don't assume all IO APICs in the system are the same.
1318 1319 *
1319 1320 * Set to the minimum version.
1320 1321 */
1321 1322 for (i = 0; i < apic_io_max; i++) {
1322 1323 if ((apic_io_ver[i] != 0) &&
1323 1324 ((min_io_apic_ver == 0) ||
1324 1325 (min_io_apic_ver >= apic_io_ver[i])))
1325 1326 min_io_apic_ver = apic_io_ver[i];
1326 1327 }
1327 1328
1328 1329 /* Assume all local APICs are of the same version. */
1329 1330 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1330 1331 }
1331 1332 return (version);
1332 1333 }
1333 1334
1334 1335 static struct apic_mpfps_hdr *
1335 1336 apic_find_fps_sig(caddr_t cptr, int len)
1336 1337 {
1337 1338 int i;
1338 1339
1339 1340 /* Look for the pattern "_MP_" */
1340 1341 for (i = 0; i < len; i += 16) {
1341 1342 if ((*(cptr+i) == '_') &&
1342 1343 (*(cptr+i+1) == 'M') &&
1343 1344 (*(cptr+i+2) == 'P') &&
1344 1345 (*(cptr+i+3) == '_'))
1345 1346 /*LINTED: pointer cast may result in improper alignment */
1346 1347 return ((struct apic_mpfps_hdr *)(cptr + i));
1347 1348 }
1348 1349 return (NULL);
1349 1350 }
1350 1351
1351 1352 static int
1352 1353 apic_checksum(caddr_t bptr, int len)
1353 1354 {
1354 1355 int i;
1355 1356 uchar_t cksum;
1356 1357
1357 1358 cksum = 0;
1358 1359 for (i = 0; i < len; i++)
1359 1360 cksum += *bptr++;
1360 1361 return ((int)cksum);
1361 1362 }
1362 1363
1363 1364 /*
1364 1365 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1365 1366 * needs special handling. We may need to chase up the device tree,
1366 1367 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1367 1368 * to find the IPIN at the root bus that relates to the IPIN on the
1368 1369 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1369 1370 * in the MP table or the ACPI namespace for this device itself.
1370 1371 * We handle both cases in the search below.
1371 1372 */
1372 1373 /* this is the non-acpi version */
1373 1374 int
1374 1375 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1375 1376 struct apic_io_intr **intrp)
1376 1377 {
1377 1378 dev_info_t *dipp, *dip;
1378 1379 int pci_irq;
1379 1380 ddi_acc_handle_t cfg_handle;
1380 1381 int bridge_devno, bridge_bus;
1381 1382 int ipin;
1382 1383
1383 1384 dip = idip;
1384 1385
1385 1386 /*CONSTCOND*/
1386 1387 while (1) {
1387 1388 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1388 1389 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1389 1390 return (-1);
1390 1391 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1391 1392 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1392 1393 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1393 1394 pci_config_teardown(&cfg_handle);
1394 1395 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1395 1396 NULL) != 0)
1396 1397 return (-1);
1397 1398 /*
1398 1399 * This is the rotating scheme documented in the
1399 1400 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1400 1401 * behind another PCI-to-PCI bridge, then it needs
1401 1402 * to keep ascending until an interrupt entry is
1402 1403 * found or the root is reached.
1403 1404 */
1404 1405 ipin = (child_devno + child_ipin) % PCI_INTD;
1405 1406 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1406 1407 bridge_bus = (int)apic_single_pci_busid;
1407 1408 pci_irq = ((bridge_devno & 0x1f) << 2) |
1408 1409 (ipin & 0x3);
1409 1410 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1410 1411 bridge_bus)) != NULL) {
1411 1412 return (pci_irq);
1412 1413 }
1413 1414 dip = dipp;
1414 1415 child_devno = bridge_devno;
1415 1416 child_ipin = ipin;
1416 1417 } else {
1417 1418 pci_config_teardown(&cfg_handle);
1418 1419 return (-1);
1419 1420 }
1420 1421 }
1421 1422 /*LINTED: function will not fall off the bottom */
1422 1423 }
1423 1424
1424 1425 uchar_t
1425 1426 acpi_find_ioapic(int irq)
1426 1427 {
1427 1428 int i;
1428 1429
1429 1430 for (i = 0; i < apic_io_max; i++) {
1430 1431 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1431 1432 return ((uchar_t)i);
1432 1433 }
1433 1434 return (0xFF); /* shouldn't happen */
1434 1435 }
1435 1436
1436 1437 /*
1437 1438 * See if two irqs are compatible for sharing a vector.
1438 1439 * Currently we only support sharing of PCI devices.
1439 1440 */
1440 1441 static int
1441 1442 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1442 1443 {
1443 1444 uint_t level1, po1;
1444 1445 uint_t level2, po2;
1445 1446
1446 1447 /* Assume active high by default */
1447 1448 po1 = 0;
1448 1449 po2 = 0;
1449 1450
1450 1451 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1451 1452 return (0);
1452 1453
1453 1454 if (iflag1.intr_el == INTR_EL_CONFORM)
1454 1455 level1 = AV_LEVEL;
1455 1456 else
1456 1457 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1457 1458
1458 1459 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1459 1460 (iflag1.intr_po == INTR_PO_CONFORM)))
1460 1461 po1 = AV_ACTIVE_LOW;
1461 1462
1462 1463 if (iflag2.intr_el == INTR_EL_CONFORM)
1463 1464 level2 = AV_LEVEL;
1464 1465 else
1465 1466 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1466 1467
1467 1468 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1468 1469 (iflag2.intr_po == INTR_PO_CONFORM)))
1469 1470 po2 = AV_ACTIVE_LOW;
1470 1471
1471 1472 if ((level1 == level2) && (po1 == po2))
1472 1473 return (1);
1473 1474
1474 1475 return (0);
1475 1476 }
1476 1477
1477 1478 struct apic_io_intr *
1478 1479 apic_find_io_intr_w_busid(int irqno, int busid)
1479 1480 {
1480 1481 struct apic_io_intr *intrp;
1481 1482
1482 1483 /*
1483 1484 * It can have more than 1 entry with same source bus IRQ,
1484 1485 * but unique with the source bus id
1485 1486 */
1486 1487 intrp = apic_io_intrp;
1487 1488 if (intrp != NULL) {
1488 1489 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1489 1490 if (intrp->intr_irq == irqno &&
1490 1491 intrp->intr_busid == busid &&
1491 1492 intrp->intr_type == IO_INTR_INT)
1492 1493 return (intrp);
1493 1494 intrp++;
1494 1495 }
1495 1496 }
1496 1497 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1497 1498 "busid %x:%x\n", irqno, busid));
1498 1499 return ((struct apic_io_intr *)NULL);
1499 1500 }
1500 1501
1501 1502
1502 1503 struct mps_bus_info {
1503 1504 char *bus_name;
1504 1505 int bus_id;
1505 1506 } bus_info_array[] = {
1506 1507 "ISA ", BUS_ISA,
1507 1508 "PCI ", BUS_PCI,
1508 1509 "EISA ", BUS_EISA,
1509 1510 "XPRESS", BUS_XPRESS,
1510 1511 "PCMCIA", BUS_PCMCIA,
1511 1512 "VL ", BUS_VL,
1512 1513 "CBUS ", BUS_CBUS,
1513 1514 "CBUSII", BUS_CBUSII,
1514 1515 "FUTURE", BUS_FUTURE,
1515 1516 "INTERN", BUS_INTERN,
1516 1517 "MBI ", BUS_MBI,
1517 1518 "MBII ", BUS_MBII,
1518 1519 "MPI ", BUS_MPI,
1519 1520 "MPSA ", BUS_MPSA,
1520 1521 "NUBUS ", BUS_NUBUS,
1521 1522 "TC ", BUS_TC,
1522 1523 "VME ", BUS_VME,
1523 1524 "PCI-E ", BUS_PCIE
1524 1525 };
1525 1526
1526 1527 static int
1527 1528 apic_find_bus_type(char *bus)
1528 1529 {
1529 1530 int i = 0;
1530 1531
1531 1532 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1532 1533 if (strncmp(bus, bus_info_array[i].bus_name,
1533 1534 strlen(bus_info_array[i].bus_name)) == 0)
1534 1535 return (bus_info_array[i].bus_id);
1535 1536 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1536 1537 return (0);
1537 1538 }
1538 1539
1539 1540 static int
1540 1541 apic_find_bus(int busid)
1541 1542 {
1542 1543 struct apic_bus *busp;
1543 1544
1544 1545 busp = apic_busp;
1545 1546 while (busp->bus_entry == APIC_BUS_ENTRY) {
1546 1547 if (busp->bus_id == busid)
1547 1548 return (apic_find_bus_type((char *)&busp->bus_str1));
1548 1549 busp++;
1549 1550 }
1550 1551 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1551 1552 return (0);
1552 1553 }
1553 1554
1554 1555 int
1555 1556 apic_find_bus_id(int bustype)
1556 1557 {
1557 1558 struct apic_bus *busp;
1558 1559
1559 1560 busp = apic_busp;
1560 1561 while (busp->bus_entry == APIC_BUS_ENTRY) {
1561 1562 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1562 1563 return (busp->bus_id);
1563 1564 busp++;
1564 1565 }
1565 1566 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1566 1567 bustype));
1567 1568 return (-1);
1568 1569 }
1569 1570
1570 1571 /*
1571 1572 * Check if a particular irq need to be reserved for any io_intr
1572 1573 */
1573 1574 static struct apic_io_intr *
1574 1575 apic_find_io_intr(int irqno)
1575 1576 {
1576 1577 struct apic_io_intr *intrp;
1577 1578
1578 1579 intrp = apic_io_intrp;
1579 1580 if (intrp != NULL) {
1580 1581 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1581 1582 if (intrp->intr_irq == irqno &&
1582 1583 intrp->intr_type == IO_INTR_INT)
1583 1584 return (intrp);
1584 1585 intrp++;
1585 1586 }
1586 1587 }
1587 1588 return ((struct apic_io_intr *)NULL);
1588 1589 }
1589 1590
1590 1591 /*
1591 1592 * Check if the given ioapicindex intin combination has already been assigned
1592 1593 * an irq. If so return irqno. Else -1
1593 1594 */
1594 1595 int
1595 1596 apic_find_intin(uchar_t ioapic, uchar_t intin)
1596 1597 {
1597 1598 apic_irq_t *irqptr;
1598 1599 int i;
1599 1600
1600 1601 /* find ioapic and intin in the apic_irq_table[] and return the index */
1601 1602 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1602 1603 irqptr = apic_irq_table[i];
1603 1604 while (irqptr) {
1604 1605 if ((irqptr->airq_mps_intr_index >= 0) &&
1605 1606 (irqptr->airq_intin_no == intin) &&
1606 1607 (irqptr->airq_ioapicindex == ioapic)) {
1607 1608 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1608 1609 "entry for ioapic:intin %x:%x "
1609 1610 "shared interrupts ?", ioapic, intin));
1610 1611 return (i);
1611 1612 }
1612 1613 irqptr = irqptr->airq_next;
1613 1614 }
1614 1615 }
1615 1616 return (-1);
1616 1617 }
1617 1618
1618 1619 int
1619 1620 apic_allocate_irq(int irq)
1620 1621 {
1621 1622 int freeirq, i;
1622 1623
1623 1624 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1624 1625 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1625 1626 (irq - 1))) == -1) {
1626 1627 /*
1627 1628 * if BIOS really defines every single irq in the mps
1628 1629 * table, then don't worry about conflicting with
1629 1630 * them, just use any free slot in apic_irq_table
1630 1631 */
1631 1632 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1632 1633 if ((apic_irq_table[i] == NULL) ||
1633 1634 apic_irq_table[i]->airq_mps_intr_index ==
1634 1635 FREE_INDEX) {
1635 1636 freeirq = i;
1636 1637 break;
1637 1638 }
1638 1639 }
1639 1640 if (freeirq == -1) {
1640 1641 /* This shouldn't happen, but just in case */
1641 1642 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1642 1643 return (-1);
1643 1644 }
1644 1645 }
1645 1646 if (apic_irq_table[freeirq] == NULL) {
1646 1647 apic_irq_table[freeirq] =
1647 1648 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1648 1649 if (apic_irq_table[freeirq] == NULL) {
1649 1650 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1650 1651 psm_name);
1651 1652 return (-1);
1652 1653 }
1653 1654 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1654 1655 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1655 1656 }
1656 1657 return (freeirq);
1657 1658 }
1658 1659
1659 1660 static int
1660 1661 apic_find_free_irq(int start, int end)
1661 1662 {
1662 1663 int i;
1663 1664
1664 1665 for (i = start; i <= end; i++)
1665 1666 /* Check if any I/O entry needs this IRQ */
1666 1667 if (apic_find_io_intr(i) == NULL) {
1667 1668 /* Then see if it is free */
1668 1669 if ((apic_irq_table[i] == NULL) ||
1669 1670 (apic_irq_table[i]->airq_mps_intr_index ==
1670 1671 FREE_INDEX)) {
1671 1672 return (i);
1672 1673 }
1673 1674 }
1674 1675 return (-1);
1675 1676 }
1676 1677
1677 1678 /*
1678 1679 * compute the polarity, trigger mode and vector for programming into
1679 1680 * the I/O apic and record in airq_rdt_entry.
1680 1681 */
1681 1682 void
1682 1683 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1683 1684 {
1684 1685 int ioapicindex, bus_type, vector;
1685 1686 short intr_index;
1686 1687 uint_t level, po, io_po;
1687 1688 struct apic_io_intr *iointrp;
1688 1689
1689 1690 intr_index = irqptr->airq_mps_intr_index;
1690 1691 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1691 1692 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1692 1693 (void *)irqptr->airq_dip, irqptr->airq_vector));
1693 1694
1694 1695 if (intr_index == RESERVE_INDEX) {
1695 1696 apic_error |= APIC_ERR_INVALID_INDEX;
1696 1697 return;
1697 1698 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1698 1699 return;
1699 1700 }
1700 1701
1701 1702 vector = irqptr->airq_vector;
1702 1703 ioapicindex = irqptr->airq_ioapicindex;
1703 1704 /* Assume edge triggered by default */
1704 1705 level = 0;
1705 1706 /* Assume active high by default */
1706 1707 po = 0;
1707 1708
1708 1709 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1709 1710 ASSERT(irq < 16);
1710 1711 if (eisa_level_intr_mask & (1 << irq))
1711 1712 level = AV_LEVEL;
1712 1713 if (intr_index == FREE_INDEX && apic_defconf == 0)
1713 1714 apic_error |= APIC_ERR_INVALID_INDEX;
1714 1715 } else if (intr_index == ACPI_INDEX) {
1715 1716 bus_type = irqptr->airq_iflag.bustype;
1716 1717 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1717 1718 if (bus_type == BUS_PCI)
1718 1719 level = AV_LEVEL;
1719 1720 } else
1720 1721 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1721 1722 AV_LEVEL : 0;
1722 1723 if (level &&
1723 1724 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1724 1725 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1725 1726 bus_type == BUS_PCI)))
1726 1727 po = AV_ACTIVE_LOW;
1727 1728 } else {
1728 1729 iointrp = apic_io_intrp + intr_index;
1729 1730 bus_type = apic_find_bus(iointrp->intr_busid);
1730 1731 if (iointrp->intr_el == INTR_EL_CONFORM) {
1731 1732 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1732 1733 level = AV_LEVEL;
1733 1734 else if (bus_type == BUS_PCI)
1734 1735 level = AV_LEVEL;
1735 1736 } else
1736 1737 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1737 1738 AV_LEVEL : 0;
1738 1739 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1739 1740 (iointrp->intr_po == INTR_PO_CONFORM &&
1740 1741 bus_type == BUS_PCI)))
1741 1742 po = AV_ACTIVE_LOW;
1742 1743 }
1743 1744 if (level)
1744 1745 apic_level_intr[irq] = 1;
1745 1746 /*
1746 1747 * The 82489DX External APIC cannot do active low polarity interrupts.
1747 1748 */
1748 1749 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1749 1750 io_po = po;
1750 1751 else
1751 1752 io_po = 0;
1752 1753
1753 1754 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1754 1755 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1755 1756 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1756 1757 irqptr->airq_intin_no, level, io_po, vector,
1757 1758 irqptr->airq_cpu);
1758 1759
1759 1760 irqptr->airq_rdt_entry = level|io_po|vector;
1760 1761 }
1761 1762
1762 1763 int
1763 1764 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1764 1765 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1765 1766 {
1766 1767
1767 1768 int status;
1768 1769 acpi_psm_lnk_t acpipsmlnk;
1769 1770
1770 1771 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1771 1772 intr_flagp)) == ACPI_PSM_SUCCESS) {
1772 1773 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1773 1774 "from cache for device %s, instance #%d\n", psm_name,
1774 1775 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1775 1776 return (status);
1776 1777 }
1777 1778
1778 1779 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1779 1780
1780 1781 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1781 1782 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1782 1783 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1783 1784 " acpi_translate_pci_irq failed for device %s, instance"
1784 1785 " #%d", psm_name, ddi_get_name(dip),
1785 1786 ddi_get_instance(dip)));
1786 1787 return (status);
1787 1788 }
1788 1789
1789 1790 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1790 1791 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1791 1792 intr_flagp);
1792 1793 if (status != ACPI_PSM_SUCCESS) {
1793 1794 status = acpi_get_current_irq_resource(&acpipsmlnk,
1794 1795 pci_irqp, intr_flagp);
1795 1796 }
1796 1797 }
1797 1798
1798 1799 if (status == ACPI_PSM_SUCCESS) {
1799 1800 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1800 1801 intr_flagp, &acpipsmlnk);
1801 1802
1802 1803 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1803 1804 "new irq %d for device %s, instance #%d\n", psm_name,
1804 1805 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1805 1806 }
1806 1807
1807 1808 return (status);
1808 1809 }
1809 1810
1810 1811 /*
1811 1812 * Adds an entry to the irq list passed in, and returns the new list.
1812 1813 * Entries are added in priority order (lower numerical priorities are
1813 1814 * placed closer to the head of the list)
1814 1815 */
1815 1816 static prs_irq_list_t *
1816 1817 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1817 1818 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1818 1819 {
1819 1820 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1820 1821
1821 1822 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1822 1823
1823 1824 newent->list_prio = priority;
1824 1825 newent->irq = irq;
1825 1826 newent->intrflags = *iflagp;
1826 1827 newent->prsprv = *prsprvp;
1827 1828 /* ->next is NULL from kmem_zalloc */
1828 1829
1829 1830 /*
1830 1831 * New list -- return the new entry as the list.
1831 1832 */
1832 1833 if (listp == NULL)
1833 1834 return (newent);
1834 1835
1835 1836 /*
1836 1837 * Save original list pointer for return (since we're not modifying
1837 1838 * the head)
1838 1839 */
1839 1840 origlistp = listp;
1840 1841
1841 1842 /*
1842 1843 * Insertion sort, with entries with identical keys stored AFTER
1843 1844 * existing entries (the less-than-or-equal test of priority does
1844 1845 * this for us).
1845 1846 */
1846 1847 while (listp != NULL && listp->list_prio <= priority) {
1847 1848 prevp = listp;
1848 1849 listp = listp->next;
1849 1850 }
1850 1851
1851 1852 newent->next = listp;
1852 1853
1853 1854 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1854 1855 return (newent);
1855 1856 } else {
1856 1857 prevp->next = newent;
1857 1858 return (origlistp);
1858 1859 }
1859 1860 }
1860 1861
1861 1862 /*
1862 1863 * Frees the list passed in, deallocating all memory and leaving *listpp
1863 1864 * set to NULL.
1864 1865 */
1865 1866 static void
1866 1867 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1867 1868 {
1868 1869 struct prs_irq_list_ent *nextp;
1869 1870
1870 1871 ASSERT(listpp != NULL);
1871 1872
1872 1873 while (*listpp != NULL) {
1873 1874 nextp = (*listpp)->next;
1874 1875 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1875 1876 *listpp = nextp;
1876 1877 }
1877 1878 }
1878 1879
1879 1880 /*
1880 1881 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1881 1882 * irqs returned by the link device's _PRS method. The irqs are chosen
1882 1883 * to minimize contention in situations where the interrupt link device
1883 1884 * can be programmed to steer interrupts to different interrupt controller
1884 1885 * inputs (some of which may already be in use). The list is sorted in order
1885 1886 * of irqs to use, with the highest priority given to interrupt controller
1886 1887 * inputs that are not shared. When an interrupt controller input
1887 1888 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1888 1889 * returned list in the order that minimizes sharing (thereby ensuring lowest
1889 1890 * possible latency from interrupt trigger time to ISR execution time).
1890 1891 */
1891 1892 static prs_irq_list_t *
1892 1893 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1893 1894 int crs_irq)
1894 1895 {
1895 1896 int32_t irq;
1896 1897 int i;
1897 1898 prs_irq_list_t *prsirqlistp = NULL;
1898 1899 iflag_t iflags;
1899 1900
1900 1901 while (irqlistent != NULL) {
1901 1902 irqlistent->intr_flags.bustype = BUS_PCI;
1902 1903
1903 1904 for (i = 0; i < irqlistent->num_irqs; i++) {
1904 1905
1905 1906 irq = irqlistent->irqs[i];
1906 1907
1907 1908 if (irq <= 0) {
1908 1909 /* invalid irq number */
1909 1910 continue;
1910 1911 }
1911 1912
1912 1913 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1913 1914 continue;
1914 1915
1915 1916 if ((apic_irq_table[irq] == NULL) ||
1916 1917 (apic_irq_table[irq]->airq_dip == dip)) {
1917 1918
1918 1919 prsirqlistp = acpi_insert_prs_irq_ent(
1919 1920 prsirqlistp, 0 /* Highest priority */, irq,
1920 1921 &irqlistent->intr_flags,
1921 1922 &irqlistent->acpi_prs_prv);
1922 1923
1923 1924 /*
1924 1925 * If we do not prefer the current irq from _CRS
1925 1926 * or if we do and this irq is the same as the
1926 1927 * current irq from _CRS, this is the one
1927 1928 * to pick.
1928 1929 */
1929 1930 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1930 1931 return (prsirqlistp);
1931 1932 }
1932 1933 continue;
1933 1934 }
1934 1935
1935 1936 /*
1936 1937 * Edge-triggered interrupts cannot be shared
1937 1938 */
1938 1939 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1939 1940 continue;
1940 1941
1941 1942 /*
1942 1943 * To work around BIOSes that contain incorrect
1943 1944 * interrupt polarity information in interrupt
1944 1945 * descriptors returned by _PRS, we assume that
1945 1946 * the polarity of the other device sharing this
1946 1947 * interrupt controller input is compatible.
1947 1948 * If it's not, the caller will catch it when
1948 1949 * the caller invokes the link device's _CRS method
1949 1950 * (after invoking its _SRS method).
1950 1951 */
1951 1952 iflags = irqlistent->intr_flags;
1952 1953 iflags.intr_po =
1953 1954 apic_irq_table[irq]->airq_iflag.intr_po;
1954 1955
1955 1956 if (!acpi_intr_compatible(iflags,
1956 1957 apic_irq_table[irq]->airq_iflag)) {
1957 1958 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1958 1959 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1959 1960 psm_name, irq,
1960 1961 iflags.intr_po,
1961 1962 iflags.intr_el,
1962 1963 iflags.bustype,
1963 1964 apic_irq_table[irq]->airq_iflag.intr_po,
1964 1965 apic_irq_table[irq]->airq_iflag.intr_el,
1965 1966 apic_irq_table[irq]->airq_iflag.bustype));
1966 1967 continue;
1967 1968 }
1968 1969
1969 1970 /*
1970 1971 * If we prefer the irq from _CRS, no need
1971 1972 * to search any further (and make sure
1972 1973 * to add this irq with the highest priority
1973 1974 * so it's tried first).
1974 1975 */
1975 1976 if (crs_irq == irq && apic_prefer_crs) {
1976 1977
1977 1978 return (acpi_insert_prs_irq_ent(
1978 1979 prsirqlistp,
1979 1980 0 /* Highest priority */,
1980 1981 irq, &iflags,
1981 1982 &irqlistent->acpi_prs_prv));
1982 1983 }
1983 1984
1984 1985 /*
1985 1986 * Priority is equal to the share count (lower
1986 1987 * share count is higher priority). Note that
1987 1988 * the intr flags passed in here are the ones we
1988 1989 * changed above -- if incorrect, it will be
1989 1990 * caught by the caller's _CRS flags comparison.
1990 1991 */
1991 1992 prsirqlistp = acpi_insert_prs_irq_ent(
1992 1993 prsirqlistp,
1993 1994 apic_irq_table[irq]->airq_share, irq,
1994 1995 &iflags, &irqlistent->acpi_prs_prv);
1995 1996 }
1996 1997
1997 1998 /* Go to the next irqlist entry */
1998 1999 irqlistent = irqlistent->next;
1999 2000 }
2000 2001
2001 2002 return (prsirqlistp);
2002 2003 }
2003 2004
2004 2005 /*
2005 2006 * Configures the irq for the interrupt link device identified by
2006 2007 * acpipsmlnkp.
2007 2008 *
2008 2009 * Gets the current and the list of possible irq settings for the
2009 2010 * device. If apic_unconditional_srs is not set, and the current
2010 2011 * resource setting is in the list of possible irq settings,
2011 2012 * current irq resource setting is passed to the caller.
2012 2013 *
2013 2014 * Otherwise, picks an irq number from the list of possible irq
2014 2015 * settings, and sets the irq of the device to this value.
2015 2016 * If prefer_crs is set, among a set of irq numbers in the list that have
2016 2017 * the least number of devices sharing the interrupt, we pick current irq
2017 2018 * resource setting if it is a member of this set.
2018 2019 *
2019 2020 * Passes the irq number in the value pointed to by pci_irqp, and
2020 2021 * polarity and sensitivity in the structure pointed to by dipintrflagp
2021 2022 * to the caller.
2022 2023 *
2023 2024 * Note that if setting the irq resource failed, but successfuly obtained
2024 2025 * the current irq resource settings, passes the current irq resources
2025 2026 * and considers it a success.
2026 2027 *
2027 2028 * Returns:
2028 2029 * ACPI_PSM_SUCCESS on success.
2029 2030 *
2030 2031 * ACPI_PSM_FAILURE if an error occured during the configuration or
2031 2032 * if a suitable irq was not found for this device, or if setting the
2032 2033 * irq resource and obtaining the current resource fails.
2033 2034 *
2034 2035 */
2035 2036 static int
2036 2037 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2037 2038 int *pci_irqp, iflag_t *dipintr_flagp)
2038 2039 {
2039 2040 int32_t irq;
2040 2041 int cur_irq = -1;
2041 2042 acpi_irqlist_t *irqlistp;
2042 2043 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2043 2044 boolean_t found_irq = B_FALSE;
2044 2045
2045 2046 dipintr_flagp->bustype = BUS_PCI;
2046 2047
2047 2048 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2048 2049 == ACPI_PSM_FAILURE) {
2049 2050 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2050 2051 "or assign IRQ for device %s, instance #%d: The system was "
2051 2052 "unable to get the list of potential IRQs from ACPI.",
2052 2053 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2053 2054
2054 2055 return (ACPI_PSM_FAILURE);
2055 2056 }
2056 2057
2057 2058 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2058 2059 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2059 2060 (cur_irq > 0)) {
2060 2061 /*
2061 2062 * If an IRQ is set in CRS and that IRQ exists in the set
2062 2063 * returned from _PRS, return that IRQ, otherwise print
2063 2064 * a warning
2064 2065 */
2065 2066
2066 2067 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2067 2068 == ACPI_PSM_SUCCESS) {
2068 2069
2069 2070 ASSERT(pci_irqp != NULL);
2070 2071 *pci_irqp = cur_irq;
2071 2072 acpi_free_irqlist(irqlistp);
2072 2073 return (ACPI_PSM_SUCCESS);
2073 2074 }
2074 2075
2075 2076 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2076 2077 "current irq %d for device %s, instance #%d in ACPI's "
2077 2078 "list of possible irqs for this device. Picking one from "
2078 2079 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2079 2080 ddi_get_instance(dip)));
2080 2081 }
2081 2082
2082 2083 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2083 2084 cur_irq)) == NULL) {
2084 2085
2085 2086 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2086 2087 "suitable irq from the list of possible irqs for device "
2087 2088 "%s, instance #%d in ACPI's list of possible irqs",
2088 2089 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2089 2090
2090 2091 acpi_free_irqlist(irqlistp);
2091 2092 return (ACPI_PSM_FAILURE);
2092 2093 }
2093 2094
2094 2095 acpi_free_irqlist(irqlistp);
2095 2096
2096 2097 for (prs_irq_entp = prs_irq_listp;
2097 2098 prs_irq_entp != NULL && found_irq == B_FALSE;
2098 2099 prs_irq_entp = prs_irq_entp->next) {
2099 2100
2100 2101 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2101 2102 irq = prs_irq_entp->irq;
2102 2103
2103 2104 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2104 2105 "device %s instance #%d\n", psm_name, irq,
2105 2106 ddi_get_name(dip), ddi_get_instance(dip)));
2106 2107
2107 2108 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2108 2109 == ACPI_PSM_SUCCESS) {
2109 2110 /*
2110 2111 * setting irq was successful, check to make sure CRS
2111 2112 * reflects that. If CRS does not agree with what we
2112 2113 * set, return the irq that was set.
2113 2114 */
2114 2115
2115 2116 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2116 2117 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2117 2118
2118 2119 if (cur_irq != irq)
2119 2120 APIC_VERBOSE_IRQ((CE_WARN,
2120 2121 "!%s: IRQ resource set "
2121 2122 "(irqno %d) for device %s "
2122 2123 "instance #%d, differs from "
2123 2124 "current setting irqno %d",
2124 2125 psm_name, irq, ddi_get_name(dip),
2125 2126 ddi_get_instance(dip), cur_irq));
2126 2127 } else {
2127 2128 /*
2128 2129 * On at least one system, there was a bug in
2129 2130 * a DSDT method called by _STA, causing _STA to
2130 2131 * indicate that the link device was disabled
2131 2132 * (when, in fact, it was enabled). Since _SRS
2132 2133 * succeeded, assume that _CRS is lying and use
2133 2134 * the iflags from this _PRS interrupt choice.
2134 2135 * If we're wrong about the flags, the polarity
2135 2136 * will be incorrect and we may get an interrupt
2136 2137 * storm, but there's not much else we can do
2137 2138 * at this point.
2138 2139 */
2139 2140 *dipintr_flagp = prs_irq_entp->intrflags;
2140 2141 }
2141 2142
2142 2143 /*
2143 2144 * Return the irq that was set, and not what _CRS
2144 2145 * reports, since _CRS has been seen to return
2145 2146 * different IRQs than what was passed to _SRS on some
2146 2147 * systems (and just not return successfully on others).
2147 2148 */
2148 2149 cur_irq = irq;
2149 2150 found_irq = B_TRUE;
2150 2151 } else {
2151 2152 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2152 2153 "irq %d failed for device %s instance #%d",
2153 2154 psm_name, irq, ddi_get_name(dip),
2154 2155 ddi_get_instance(dip)));
2155 2156
2156 2157 if (cur_irq == -1) {
2157 2158 acpi_destroy_prs_irq_list(&prs_irq_listp);
2158 2159 return (ACPI_PSM_FAILURE);
2159 2160 }
2160 2161 }
2161 2162 }
2162 2163
2163 2164 acpi_destroy_prs_irq_list(&prs_irq_listp);
2164 2165
2165 2166 if (!found_irq)
2166 2167 return (ACPI_PSM_FAILURE);
2167 2168
2168 2169 ASSERT(pci_irqp != NULL);
2169 2170 *pci_irqp = cur_irq;
2170 2171 return (ACPI_PSM_SUCCESS);
2171 2172 }
2172 2173
2173 2174 void
2174 2175 ioapic_disable_redirection()
2175 2176 {
2176 2177 int ioapic_ix;
2177 2178 int intin_max;
2178 2179 int intin_ix;
2179 2180
2180 2181 /* Disable the I/O APIC redirection entries */
2181 2182 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2182 2183
2183 2184 /* Bits 23-16 define the maximum redirection entries */
2184 2185 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2185 2186 & 0xff;
2186 2187
2187 2188 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2188 2189 /*
2189 2190 * The assumption here is that this is safe, even for
2190 2191 * systems with IOAPICs that suffer from the hardware
2191 2192 * erratum because all devices have been quiesced before
2192 2193 * this function is called from apic_shutdown()
2193 2194 * (or equivalent). If that assumption turns out to be
2194 2195 * false, this mask operation can induce the same
2195 2196 * erratum result we're trying to avoid.
2196 2197 */
2197 2198 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2198 2199 AV_MASK);
2199 2200 }
2200 2201 }
2201 2202 }
2202 2203
2203 2204 /*
2204 2205 * Looks for an IOAPIC with the specified physical address in the /ioapics
2205 2206 * node in the device tree (created by the PCI enumerator).
2206 2207 */
2207 2208 static boolean_t
2208 2209 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2209 2210 {
2210 2211 /*
2211 2212 * Look in /ioapics, for the ioapic with
2212 2213 * the physical address given
2213 2214 */
2214 2215 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2215 2216 dev_info_t *ioapic_child;
2216 2217 boolean_t rv = B_FALSE;
2217 2218 int vid, did;
2218 2219 uint64_t ioapic_paddr;
2219 2220 boolean_t done = B_FALSE;
2220 2221
2221 2222 if (ioapicsnode == NULL)
2222 2223 return (B_FALSE);
2223 2224
2224 2225 /* Load first child: */
2225 2226 ioapic_child = ddi_get_child(ioapicsnode);
2226 2227 while (!done && ioapic_child != 0) { /* Iterate over children */
2227 2228
2228 2229 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2229 2230 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2230 2231 != 0 && physaddr == ioapic_paddr) {
2231 2232
2232 2233 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2233 2234 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2234 2235
2235 2236 if (vid == VENID_AMD) {
2236 2237
2237 2238 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2238 2239 ioapic_child, DDI_PROP_DONTPASS,
2239 2240 IOAPICS_PROP_DEVID, 0);
2240 2241
2241 2242 if (did == DEVID_8131_IOAPIC ||
2242 2243 did == DEVID_8132_IOAPIC) {
2243 2244 rv = B_TRUE;
2244 2245 done = B_TRUE;
2245 2246 }
2246 2247 }
2247 2248 }
2248 2249
2249 2250 if (!done)
2250 2251 ioapic_child = ddi_get_next_sibling(ioapic_child);
2251 2252 }
2252 2253
2253 2254 /* The ioapics node was held by ddi_find_devinfo, so release it */
2254 2255 ndi_rele_devi(ioapicsnode);
2255 2256 return (rv);
2256 2257 }
2257 2258
2258 2259 struct apic_state {
2259 2260 int32_t as_task_reg;
2260 2261 int32_t as_dest_reg;
2261 2262 int32_t as_format_reg;
2262 2263 int32_t as_local_timer;
2263 2264 int32_t as_pcint_vect;
2264 2265 int32_t as_int_vect0;
2265 2266 int32_t as_int_vect1;
2266 2267 int32_t as_err_vect;
2267 2268 int32_t as_init_count;
2268 2269 int32_t as_divide_reg;
2269 2270 int32_t as_spur_int_reg;
2270 2271 uint32_t as_ioapic_ids[MAX_IO_APIC];
2271 2272 };
2272 2273
2273 2274
2274 2275 static int
2275 2276 apic_acpi_enter_apicmode(void)
2276 2277 {
2277 2278 ACPI_OBJECT_LIST arglist;
2278 2279 ACPI_OBJECT arg;
2279 2280 ACPI_STATUS status;
2280 2281
2281 2282 /* Setup parameter object */
2282 2283 arglist.Count = 1;
2283 2284 arglist.Pointer = &arg;
2284 2285 arg.Type = ACPI_TYPE_INTEGER;
2285 2286 arg.Integer.Value = ACPI_APIC_MODE;
2286 2287
2287 2288 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2288 2289 /*
2289 2290 * Per ACPI spec - section 5.8.1 _PIC Method
2290 2291 * calling the \_PIC control method is optional for the OS
2291 2292 * and might not be found. It's ok to not fail in such cases.
2292 2293 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2293 2294 */
2294 2295 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2295 2296 cmn_err(CE_NOTE,
2296 2297 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2297 2298 ACPI_FAILURE(status));
2298 2299 return (PSM_FAILURE);
2299 2300 } else {
2300 2301 return (PSM_SUCCESS);
2301 2302 }
2302 2303 }
2303 2304
2304 2305
2305 2306 static void
2306 2307 apic_save_state(struct apic_state *sp)
2307 2308 {
2308 2309 int i, cpuid;
2309 2310 ulong_t iflag;
2310 2311
2311 2312 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2312 2313 /*
2313 2314 * First the local APIC.
2314 2315 */
2315 2316 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2316 2317 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2317 2318 if (apic_mode == LOCAL_APIC)
2318 2319 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2319 2320 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2320 2321 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2321 2322 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2322 2323 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2323 2324 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2324 2325 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2325 2326 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2326 2327 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2327 2328
2328 2329 /*
2329 2330 * If on the boot processor then save the IOAPICs' IDs
2330 2331 */
2331 2332 if ((cpuid = psm_get_cpu_id()) == 0) {
2332 2333
2333 2334 iflag = intr_clear();
2334 2335 lock_set(&apic_ioapic_lock);
2335 2336
2336 2337 for (i = 0; i < apic_io_max; i++)
2337 2338 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2338 2339
2339 2340 lock_clear(&apic_ioapic_lock);
2340 2341 intr_restore(iflag);
2341 2342 }
2342 2343
2343 2344 /* apic_state() is currently invoked only in Suspend/Resume */
2344 2345 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2345 2346 }
2346 2347
2347 2348 static void
2348 2349 apic_restore_state(struct apic_state *sp)
2349 2350 {
2350 2351 int i;
2351 2352 ulong_t iflag;
2352 2353
2353 2354 /*
2354 2355 * First the local APIC.
2355 2356 */
2356 2357 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2357 2358 if (apic_mode == LOCAL_APIC) {
2358 2359 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2359 2360 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2360 2361 }
2361 2362 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2362 2363 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2363 2364 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2364 2365 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2365 2366 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2366 2367 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2367 2368 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2368 2369 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2369 2370
2370 2371 /*
2371 2372 * the following only needs to be done once, so we do it on the
2372 2373 * boot processor, since we know that we only have one of those
2373 2374 */
2374 2375 if (psm_get_cpu_id() == 0) {
2375 2376
2376 2377 iflag = intr_clear();
2377 2378 lock_set(&apic_ioapic_lock);
2378 2379
2379 2380 /* Restore IOAPICs' APIC IDs */
2380 2381 for (i = 0; i < apic_io_max; i++) {
2381 2382 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2382 2383 }
2383 2384
2384 2385 lock_clear(&apic_ioapic_lock);
2385 2386 intr_restore(iflag);
2386 2387
2387 2388 /*
2388 2389 * Reenter APIC mode before restoring LNK devices
2389 2390 */
2390 2391 (void) apic_acpi_enter_apicmode();
2391 2392
2392 2393 /*
2393 2394 * restore acpi link device mappings
2394 2395 */
2395 2396 acpi_restore_link_devices();
2396 2397 }
2397 2398 }
2398 2399
2399 2400 /*
2400 2401 * Returns 0 on success
2401 2402 */
2402 2403 int
2403 2404 apic_state(psm_state_request_t *rp)
2404 2405 {
2405 2406 PMD(PMD_SX, ("apic_state "))
2406 2407 switch (rp->psr_cmd) {
2407 2408 case PSM_STATE_ALLOC:
2408 2409 rp->req.psm_state_req.psr_state =
2409 2410 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2410 2411 if (rp->req.psm_state_req.psr_state == NULL)
2411 2412 return (ENOMEM);
2412 2413 rp->req.psm_state_req.psr_state_size =
2413 2414 sizeof (struct apic_state);
2414 2415 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2415 2416 rp->req.psm_state_req.psr_state,
2416 2417 rp->req.psm_state_req.psr_state_size))
2417 2418 return (0);
2418 2419
2419 2420 case PSM_STATE_FREE:
2420 2421 kmem_free(rp->req.psm_state_req.psr_state,
2421 2422 rp->req.psm_state_req.psr_state_size);
2422 2423 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2423 2424 rp->req.psm_state_req.psr_state,
2424 2425 rp->req.psm_state_req.psr_state_size))
2425 2426 return (0);
2426 2427
2427 2428 case PSM_STATE_SAVE:
2428 2429 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2429 2430 rp->req.psm_state_req.psr_state,
2430 2431 rp->req.psm_state_req.psr_state_size))
2431 2432 apic_save_state(rp->req.psm_state_req.psr_state);
2432 2433 return (0);
2433 2434
2434 2435 case PSM_STATE_RESTORE:
2435 2436 apic_restore_state(rp->req.psm_state_req.psr_state);
2436 2437 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2437 2438 rp->req.psm_state_req.psr_state,
2438 2439 rp->req.psm_state_req.psr_state_size))
2439 2440 return (0);
2440 2441
2441 2442 default:
2442 2443 return (EINVAL);
2443 2444 }
2444 2445 }
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