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8626 make pcplusmp and apix warning-free
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2017, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
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101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 +#define UCHAR_MAX UINT8_MAX
112 +
111 113 /*
112 114 * The following vector assignments influence the value of ipltopri and
113 115 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 116 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 117 * we care to do so in future. Note some IPLs which are rarely used
116 118 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 119 * a wide range.
118 120 *
119 121 * This array is used to initialize apic_ipls[] (in apic_init()).
120 122 *
121 123 * IPL Vector range. as passed to intr_enter
122 124 * 0 none.
123 125 * 1,2,3 0x20-0x2f 0x0-0xf
124 126 * 4 0x30-0x3f 0x10-0x1f
125 127 * 5 0x40-0x5f 0x20-0x3f
126 128 * 6 0x60-0x7f 0x40-0x5f
127 129 * 7,8,9 0x80-0x8f 0x60-0x6f
128 130 * 10 0x90-0x9f 0x70-0x7f
129 131 * 11 0xa0-0xaf 0x80-0x8f
130 132 * ... ...
131 133 * 15 0xe0-0xef 0xc0-0xcf
132 134 * 15 0xf0-0xff 0xd0-0xdf
133 135 */
134 136 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 137 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 138 };
137 139 /*
138 140 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 141 * NOTE that this is vector as passed into intr_enter which is
140 142 * programmed vector - 0x20 (APIC_BASE_VECT)
141 143 */
142 144
143 145 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 146 /* The taskpri to be programmed into apic to mask given ipl */
145 147
146 148 /*
147 149 * Correlation of the hardware vector to the IPL in use, initialized
148 150 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
149 151 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
150 152 * connected to errata-stricken IOAPICs
151 153 */
152 154 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
153 155
154 156 /*
155 157 * Patchable global variables.
156 158 */
157 159 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
158 160 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
159 161
160 162 /*
161 163 * Local static data
162 164 */
163 165 static struct psm_ops apic_ops = {
164 166 apic_probe,
165 167
166 168 apic_init,
167 169 apic_picinit,
168 170 apic_intr_enter,
169 171 apic_intr_exit,
170 172 apic_setspl,
171 173 apic_addspl,
172 174 apic_delspl,
173 175 apic_disable_intr,
174 176 apic_enable_intr,
175 177 (int (*)(int))NULL, /* psm_softlvl_to_irq */
176 178 (void (*)(int))NULL, /* psm_set_softintr */
177 179
178 180 apic_set_idlecpu,
179 181 apic_unset_idlecpu,
180 182
181 183 apic_clkinit,
182 184 apic_getclkirq,
183 185 (void (*)(void))NULL, /* psm_hrtimeinit */
184 186 apic_gethrtime,
185 187
186 188 apic_get_next_processorid,
187 189 apic_cpu_start,
188 190 apic_post_cpu_start,
189 191 apic_shutdown,
190 192 apic_get_ipivect,
191 193 apic_send_ipi,
192 194
193 195 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
194 196 (void (*)(int, char *))NULL, /* psm_notify_error */
195 197 (void (*)(int))NULL, /* psm_notify_func */
196 198 apic_timer_reprogram,
197 199 apic_timer_enable,
198 200 apic_timer_disable,
199 201 apic_post_cyclic_setup,
200 202 apic_preshutdown,
201 203 apic_intr_ops, /* Advanced DDI Interrupt framework */
202 204 apic_state, /* save, restore apic state for S3 */
203 205 apic_cpu_ops, /* CPU control interface. */
204 206 };
205 207
206 208 struct psm_ops *psmops = &apic_ops;
207 209
208 210 static struct psm_info apic_psm_info = {
209 211 PSM_INFO_VER01_7, /* version */
210 212 PSM_OWN_EXCLUSIVE, /* ownership */
211 213 (struct psm_ops *)&apic_ops, /* operation */
212 214 APIC_PCPLUSMP_NAME, /* machine name */
213 215 "pcplusmp v1.4 compatible",
214 216 };
215 217
216 218 static void *apic_hdlp;
217 219
218 220 /* to gather intr data and redistribute */
219 221 static void apic_redistribute_compute(void);
220 222
221 223 /*
222 224 * This is the loadable module wrapper
223 225 */
224 226
225 227 int
226 228 _init(void)
227 229 {
228 230 if (apic_coarse_hrtime)
229 231 apic_ops.psm_gethrtime = &apic_gettime;
230 232 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
231 233 }
232 234
233 235 int
234 236 _fini(void)
235 237 {
236 238 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
237 239 }
238 240
239 241 int
240 242 _info(struct modinfo *modinfop)
241 243 {
242 244 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
243 245 }
244 246
245 247 static int
246 248 apic_probe(void)
247 249 {
248 250 /* check if apix is initialized */
249 251 if (apix_enable && apix_loaded())
250 252 return (PSM_FAILURE);
251 253
252 254 /*
253 255 * Check whether x2APIC mode was activated by BIOS. We don't support
254 256 * that in pcplusmp as apix normally handles that.
255 257 */
256 258 if (apic_local_mode() == LOCAL_X2APIC)
257 259 return (PSM_FAILURE);
258 260
259 261 /* continue using pcplusmp PSM */
260 262 apix_enable = 0;
261 263
262 264 return (apic_probe_common(apic_psm_info.p_mach_idstring));
263 265 }
264 266
265 267 static uchar_t
266 268 apic_xlate_vector_by_irq(uchar_t irq)
267 269 {
268 270 if (apic_irq_table[irq] == NULL)
269 271 return (0);
270 272
271 273 return (apic_irq_table[irq]->airq_vector);
272 274 }
273 275
274 276 void
275 277 apic_init(void)
276 278 {
277 279 int i;
278 280 int j = 1;
279 281
280 282 psm_get_ioapicid = apic_get_ioapicid;
281 283 psm_get_localapicid = apic_get_localapicid;
282 284 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
283 285
284 286 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
285 287 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
286 288 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
287 289 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
288 290 /* get to highest vector at the same ipl */
289 291 continue;
290 292 for (; j <= apic_vectortoipl[i]; j++) {
291 293 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
292 294 APIC_BASE_VECT;
293 295 }
294 296 }
295 297 for (; j < MAXIPL + 1; j++)
296 298 /* fill up any empty ipltopri slots */
297 299 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
298 300 apic_init_common();
299 301
300 302 #if !defined(__amd64)
301 303 if (cpuid_have_cr8access(CPU))
302 304 apic_have_32bit_cr8 = 1;
303 305 #endif
304 306 }
305 307
306 308 static void
307 309 apic_init_intr(void)
308 310 {
309 311 processorid_t cpun = psm_get_cpu_id();
310 312 uint_t nlvt;
311 313 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
312 314
313 315 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
314 316
315 317 if (apic_mode == LOCAL_APIC) {
316 318 /*
317 319 * We are running APIC in MMIO mode.
318 320 */
319 321 if (apic_flat_model) {
320 322 apic_reg_ops->apic_write(APIC_FORMAT_REG,
321 323 APIC_FLAT_MODEL);
322 324 } else {
323 325 apic_reg_ops->apic_write(APIC_FORMAT_REG,
324 326 APIC_CLUSTER_MODEL);
325 327 }
326 328
327 329 apic_reg_ops->apic_write(APIC_DEST_REG,
328 330 AV_HIGH_ORDER >> cpun);
329 331 }
330 332
331 333 if (apic_directed_EOI_supported()) {
332 334 /*
333 335 * Setting the 12th bit in the Spurious Interrupt Vector
334 336 * Register suppresses broadcast EOIs generated by the local
335 337 * APIC. The suppression of broadcast EOIs happens only when
336 338 * interrupts are level-triggered.
337 339 */
338 340 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
339 341 }
340 342
341 343 /* need to enable APIC before unmasking NMI */
342 344 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
343 345
344 346 /*
345 347 * Presence of an invalid vector with delivery mode AV_FIXED can
346 348 * cause an error interrupt, even if the entry is masked...so
347 349 * write a valid vector to LVT entries along with the mask bit
348 350 */
349 351
350 352 /* All APICs have timer and LINT0/1 */
351 353 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
352 354 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
353 355 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
354 356
355 357 /*
356 358 * On integrated APICs, the number of LVT entries is
357 359 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
358 360 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
359 361 */
360 362
361 363 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
362 364 nlvt = 3;
363 365 } else {
364 366 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
365 367 0xFF) + 1;
366 368 }
367 369
368 370 if (nlvt >= 5) {
369 371 /* Enable performance counter overflow interrupt */
370 372
371 373 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
372 374 apic_enable_cpcovf_intr = 0;
373 375 if (apic_enable_cpcovf_intr) {
374 376 if (apic_cpcovf_vect == 0) {
375 377 int ipl = APIC_PCINT_IPL;
376 378 int irq = apic_get_ipivect(ipl, -1);
377 379
378 380 ASSERT(irq != -1);
379 381 apic_cpcovf_vect =
380 382 apic_irq_table[irq]->airq_vector;
381 383 ASSERT(apic_cpcovf_vect);
382 384 (void) add_avintr(NULL, ipl,
383 385 (avfunc)kcpc_hw_overflow_intr,
384 386 "apic pcint", irq, NULL, NULL, NULL, NULL);
385 387 kcpc_hw_overflow_intr_installed = 1;
386 388 kcpc_hw_enable_cpc_intr =
387 389 apic_cpcovf_mask_clear;
388 390 }
389 391 apic_reg_ops->apic_write(APIC_PCINT_VECT,
390 392 apic_cpcovf_vect);
391 393 }
392 394 }
393 395
394 396 if (nlvt >= 6) {
395 397 /* Only mask TM intr if the BIOS apparently doesn't use it */
396 398
397 399 uint32_t lvtval;
398 400
399 401 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
400 402 if (((lvtval & AV_MASK) == AV_MASK) ||
401 403 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
402 404 apic_reg_ops->apic_write(APIC_THERM_VECT,
403 405 AV_MASK|APIC_RESV_IRQ);
404 406 }
405 407 }
406 408
407 409 /* Enable error interrupt */
408 410
409 411 if (nlvt >= 4 && apic_enable_error_intr) {
410 412 if (apic_errvect == 0) {
411 413 int ipl = 0xf; /* get highest priority intr */
412 414 int irq = apic_get_ipivect(ipl, -1);
413 415
414 416 ASSERT(irq != -1);
415 417 apic_errvect = apic_irq_table[irq]->airq_vector;
416 418 ASSERT(apic_errvect);
417 419 /*
418 420 * Not PSMI compliant, but we are going to merge
419 421 * with ON anyway
420 422 */
421 423 (void) add_avintr((void *)NULL, ipl,
422 424 (avfunc)apic_error_intr, "apic error intr",
423 425 irq, NULL, NULL, NULL, NULL);
424 426 }
425 427 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
426 428 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
427 429 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
428 430 }
429 431
430 432 /* Enable CMCI interrupt */
431 433 if (cmi_enable_cmci) {
432 434
433 435 mutex_enter(&cmci_cpu_setup_lock);
434 436 if (cmci_cpu_setup_registered == 0) {
435 437 mutex_enter(&cpu_lock);
436 438 register_cpu_setup_func(cmci_cpu_setup, NULL);
437 439 mutex_exit(&cpu_lock);
438 440 cmci_cpu_setup_registered = 1;
439 441 }
440 442 mutex_exit(&cmci_cpu_setup_lock);
441 443
442 444 if (apic_cmci_vect == 0) {
443 445 int ipl = 0x2;
444 446 int irq = apic_get_ipivect(ipl, -1);
445 447
446 448 ASSERT(irq != -1);
447 449 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
448 450 ASSERT(apic_cmci_vect);
449 451
450 452 (void) add_avintr(NULL, ipl,
451 453 (avfunc)cmi_cmci_trap,
452 454 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
453 455 }
454 456 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
455 457 }
456 458 }
457 459
458 460 static void
459 461 apic_picinit(void)
460 462 {
461 463 int i, j;
462 464 uint_t isr;
463 465
464 466 /*
465 467 * Initialize and enable interrupt remapping before apic
466 468 * hardware initialization
467 469 */
468 470 apic_intrmap_init(apic_mode);
469 471
470 472 /*
471 473 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
472 474 * bit on without clearing it with EOI. Since softint
473 475 * uses vector 0x20 to interrupt itself, so softint will
474 476 * not work on this machine. In order to fix this problem
475 477 * a check is made to verify all the isr bits are clear.
476 478 * If not, EOIs are issued to clear the bits.
477 479 */
478 480 for (i = 7; i >= 1; i--) {
479 481 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
480 482 if (isr != 0)
481 483 for (j = 0; ((j < 32) && (isr != 0)); j++)
482 484 if (isr & (1 << j)) {
483 485 apic_reg_ops->apic_write(
484 486 APIC_EOI_REG, 0);
485 487 isr &= ~(1 << j);
486 488 apic_error |= APIC_ERR_BOOT_EOI;
487 489 }
488 490 }
489 491
490 492 /* set a flag so we know we have run apic_picinit() */
491 493 apic_picinit_called = 1;
492 494 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
493 495 LOCK_INIT_CLEAR(&apic_ioapic_lock);
494 496 LOCK_INIT_CLEAR(&apic_error_lock);
495 497 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
496 498
497 499 picsetup(); /* initialise the 8259 */
498 500
499 501 /* add nmi handler - least priority nmi handler */
500 502 LOCK_INIT_CLEAR(&apic_nmi_lock);
501 503
502 504 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
503 505 "pcplusmp NMI handler", (caddr_t)NULL))
504 506 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
505 507
506 508 /*
507 509 * Check for directed-EOI capability in the local APIC.
508 510 */
509 511 if (apic_directed_EOI_supported() == 1) {
510 512 apic_set_directed_EOI_handler();
511 513 }
512 514
513 515 apic_init_intr();
514 516
515 517 /* enable apic mode if imcr present */
516 518 if (apic_imcrp) {
517 519 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
518 520 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
519 521 }
520 522
521 523 ioapic_init_intr(IOAPIC_MASK);
522 524 }
523 525
524 526 #ifdef DEBUG
525 527 void
526 528 apic_break(void)
527 529 {
528 530 }
529 531 #endif /* DEBUG */
530 532
531 533 /*
532 534 * platform_intr_enter
533 535 *
534 536 * Called at the beginning of the interrupt service routine to
535 537 * mask all level equal to and below the interrupt priority
536 538 * of the interrupting vector. An EOI should be given to
537 539 * the interrupt controller to enable other HW interrupts.
538 540 *
539 541 * Return -1 for spurious interrupts
540 542 *
541 543 */
542 544 /*ARGSUSED*/
543 545 static int
544 546 apic_intr_enter(int ipl, int *vectorp)
545 547 {
546 548 uchar_t vector;
547 549 int nipl;
548 550 int irq;
549 551 ulong_t iflag;
550 552 apic_cpus_info_t *cpu_infop;
551 553
552 554 /*
553 555 * The real vector delivered is (*vectorp + 0x20), but our caller
554 556 * subtracts 0x20 from the vector before passing it to us.
555 557 * (That's why APIC_BASE_VECT is 0x20.)
556 558 */
557 559 vector = (uchar_t)*vectorp;
558 560
559 561 /* if interrupted by the clock, increment apic_nsec_since_boot */
560 562 if (vector == apic_clkvect) {
561 563 if (!apic_oneshot) {
562 564 /* NOTE: this is not MT aware */
563 565 apic_hrtime_stamp++;
564 566 apic_nsec_since_boot += apic_nsec_per_intr;
565 567 apic_hrtime_stamp++;
566 568 last_count_read = apic_hertz_count;
567 569 apic_redistribute_compute();
568 570 }
569 571
570 572 /* We will avoid all the book keeping overhead for clock */
571 573 nipl = apic_ipls[vector];
572 574
573 575 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
574 576
575 577 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
576 578 apic_reg_ops->apic_send_eoi(0);
577 579
578 580 return (nipl);
579 581 }
580 582
581 583 cpu_infop = &apic_cpus[psm_get_cpu_id()];
582 584
583 585 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
584 586 cpu_infop->aci_spur_cnt++;
585 587 return (APIC_INT_SPURIOUS);
586 588 }
587 589
588 590 /* Check if the vector we got is really what we need */
589 591 if (apic_revector_pending) {
590 592 /*
591 593 * Disable interrupts for the duration of
592 594 * the vector translation to prevent a self-race for
593 595 * the apic_revector_lock. This cannot be done
594 596 * in apic_xlate_vector because it is recursive and
595 597 * we want the vector translation to be atomic with
596 598 * respect to other (higher-priority) interrupts.
597 599 */
598 600 iflag = intr_clear();
599 601 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
600 602 APIC_BASE_VECT;
601 603 intr_restore(iflag);
602 604 }
603 605
604 606 nipl = apic_ipls[vector];
605 607 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
606 608
607 609 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
608 610
609 611 cpu_infop->aci_current[nipl] = (uchar_t)irq;
610 612 cpu_infop->aci_curipl = (uchar_t)nipl;
611 613 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
612 614
613 615 /*
614 616 * apic_level_intr could have been assimilated into the irq struct.
615 617 * but, having it as a character array is more efficient in terms of
616 618 * cache usage. So, we leave it as is.
617 619 */
618 620 if (!apic_level_intr[irq]) {
619 621 apic_reg_ops->apic_send_eoi(0);
620 622 }
621 623
622 624 #ifdef DEBUG
623 625 APIC_DEBUG_BUF_PUT(vector);
624 626 APIC_DEBUG_BUF_PUT(irq);
625 627 APIC_DEBUG_BUF_PUT(nipl);
626 628 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
627 629 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
628 630 drv_usecwait(apic_stretch_interrupts);
629 631
630 632 if (apic_break_on_cpu == psm_get_cpu_id())
631 633 apic_break();
632 634 #endif /* DEBUG */
633 635 return (nipl);
634 636 }
635 637
636 638 /*
637 639 * This macro is a common code used by MMIO local apic and X2APIC
638 640 * local apic.
639 641 */
640 642 #define APIC_INTR_EXIT() \
641 643 { \
642 644 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
643 645 if (apic_level_intr[irq]) \
644 646 apic_reg_ops->apic_send_eoi(irq); \
645 647 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
646 648 /* ISR above current pri could not be in progress */ \
647 649 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
648 650 }
649 651
650 652 /*
651 653 * Any changes made to this function must also change X2APIC
652 654 * version of intr_exit.
653 655 */
654 656 void
655 657 apic_intr_exit(int prev_ipl, int irq)
656 658 {
657 659 apic_cpus_info_t *cpu_infop;
658 660
659 661 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
660 662
661 663 APIC_INTR_EXIT();
662 664 }
663 665
664 666 /*
665 667 * Same as apic_intr_exit() except it uses MSR rather than MMIO
666 668 * to access local apic registers.
667 669 */
668 670 void
669 671 x2apic_intr_exit(int prev_ipl, int irq)
670 672 {
671 673 apic_cpus_info_t *cpu_infop;
672 674
673 675 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
674 676 APIC_INTR_EXIT();
675 677 }
676 678
677 679 intr_exit_fn_t
678 680 psm_intr_exit_fn(void)
679 681 {
680 682 if (apic_mode == LOCAL_X2APIC)
681 683 return (x2apic_intr_exit);
682 684
683 685 return (apic_intr_exit);
684 686 }
685 687
686 688 /*
687 689 * Mask all interrupts below or equal to the given IPL.
688 690 * Any changes made to this function must also change X2APIC
689 691 * version of setspl.
690 692 */
691 693 static void
692 694 apic_setspl(int ipl)
693 695 {
694 696 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
695 697
696 698 /* interrupts at ipl above this cannot be in progress */
697 699 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
698 700 /*
699 701 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
700 702 * have enough time to come in before the priority is raised again
701 703 * during the idle() loop.
702 704 */
703 705 if (apic_setspl_delay)
704 706 (void) apic_reg_ops->apic_get_pri();
705 707 }
706 708
707 709 /*
708 710 * X2APIC version of setspl.
709 711 * Mask all interrupts below or equal to the given IPL
710 712 */
711 713 static void
712 714 x2apic_setspl(int ipl)
713 715 {
714 716 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
715 717
716 718 /* interrupts at ipl above this cannot be in progress */
717 719 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
718 720 }
719 721
720 722 /*ARGSUSED*/
721 723 static int
722 724 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
723 725 {
724 726 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
725 727 }
726 728
727 729 static int
728 730 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
729 731 {
730 732 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
731 733 }
732 734
733 735 static int
734 736 apic_post_cpu_start(void)
735 737 {
736 738 int cpun;
737 739 static int cpus_started = 1;
738 740
739 741 /* We know this CPU + BSP started successfully. */
740 742 cpus_started++;
741 743
742 744 /*
743 745 * On BSP we would have enabled X2APIC, if supported by processor,
744 746 * in acpi_probe(), but on AP we do it here.
745 747 *
746 748 * We enable X2APIC mode only if BSP is running in X2APIC & the
747 749 * local APIC mode of the current CPU is MMIO (xAPIC).
748 750 */
749 751 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
750 752 apic_local_mode() == LOCAL_APIC) {
751 753 apic_enable_x2apic();
752 754 }
753 755
754 756 /*
755 757 * Switch back to x2apic IPI sending method for performance when target
756 758 * CPU has entered x2apic mode.
757 759 */
758 760 if (apic_mode == LOCAL_X2APIC) {
759 761 apic_switch_ipi_callback(B_FALSE);
760 762 }
761 763
762 764 splx(ipltospl(LOCK_LEVEL));
763 765 apic_init_intr();
764 766
765 767 /*
766 768 * since some systems don't enable the internal cache on the non-boot
767 769 * cpus, so we have to enable them here
768 770 */
769 771 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
770 772
771 773 #ifdef DEBUG
772 774 APIC_AV_PENDING_SET();
773 775 #else
774 776 if (apic_mode == LOCAL_APIC)
775 777 APIC_AV_PENDING_SET();
776 778 #endif /* DEBUG */
777 779
778 780 /*
779 781 * We may be booting, or resuming from suspend; aci_status will
780 782 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
781 783 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
782 784 */
783 785 cpun = psm_get_cpu_id();
784 786 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
785 787
786 788 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
787 789 return (PSM_SUCCESS);
788 790 }
789 791
790 792 /*
791 793 * type == -1 indicates it is an internal request. Do not change
792 794 * resv_vector for these requests
793 795 */
794 796 static int
795 797 apic_get_ipivect(int ipl, int type)
796 798 {
797 799 uchar_t vector;
798 800 int irq;
799 801
800 802 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
801 803 if ((vector = apic_allocate_vector(ipl, irq, 1))) {
802 804 apic_irq_table[irq]->airq_mps_intr_index =
803 805 RESERVE_INDEX;
804 806 apic_irq_table[irq]->airq_vector = vector;
805 807 if (type != -1) {
806 808 apic_resv_vector[ipl] = vector;
807 809 }
808 810 return (irq);
809 811 }
810 812 }
811 813 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
812 814 return (-1); /* shouldn't happen */
813 815 }
814 816
815 817 static int
816 818 apic_getclkirq(int ipl)
817 819 {
818 820 int irq;
819 821
820 822 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
821 823 return (-1);
822 824 /*
823 825 * Note the vector in apic_clkvect for per clock handling.
824 826 */
825 827 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
826 828 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
827 829 apic_clkvect));
828 830 return (irq);
829 831 }
830 832
831 833 /*
832 834 * Try and disable all interrupts. We just assign interrupts to other
833 835 * processors based on policy. If any were bound by user request, we
834 836 * let them continue and return failure. We do not bother to check
835 837 * for cache affinity while rebinding.
836 838 */
837 839
838 840 static int
839 841 apic_disable_intr(processorid_t cpun)
840 842 {
841 843 int bind_cpu = 0, i, hardbound = 0;
842 844 apic_irq_t *irq_ptr;
843 845 ulong_t iflag;
844 846
845 847 iflag = intr_clear();
846 848 lock_set(&apic_ioapic_lock);
847 849
848 850 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
849 851 if (apic_reprogram_info[i].done == B_FALSE) {
850 852 if (apic_reprogram_info[i].bindcpu == cpun) {
851 853 /*
852 854 * CPU is busy -- it's the target of
853 855 * a pending reprogramming attempt
854 856 */
855 857 lock_clear(&apic_ioapic_lock);
856 858 intr_restore(iflag);
857 859 return (PSM_FAILURE);
858 860 }
859 861 }
860 862 }
861 863
862 864 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
863 865
864 866 apic_cpus[cpun].aci_curipl = 0;
865 867
866 868 i = apic_min_device_irq;
867 869 for (; i <= apic_max_device_irq; i++) {
868 870 /*
869 871 * If there are bound interrupts on this cpu, then
870 872 * rebind them to other processors.
871 873 */
872 874 if ((irq_ptr = apic_irq_table[i]) != NULL) {
873 875 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
874 876 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
875 877 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
876 878
877 879 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
878 880 hardbound = 1;
879 881 continue;
880 882 }
881 883
882 884 if (irq_ptr->airq_temp_cpu == cpun) {
883 885 do {
884 886 bind_cpu =
885 887 apic_find_cpu(APIC_CPU_INTR_ENABLE);
886 888 } while (apic_rebind_all(irq_ptr, bind_cpu));
887 889 }
888 890 }
889 891 }
890 892
891 893 lock_clear(&apic_ioapic_lock);
892 894 intr_restore(iflag);
893 895
894 896 if (hardbound) {
895 897 cmn_err(CE_WARN, "Could not disable interrupts on %d"
896 898 "due to user bound interrupts", cpun);
897 899 return (PSM_FAILURE);
898 900 }
899 901 else
900 902 return (PSM_SUCCESS);
901 903 }
902 904
903 905 /*
904 906 * Bind interrupts to the CPU's local APIC.
905 907 * Interrupts should not be bound to a CPU's local APIC until the CPU
906 908 * is ready to receive interrupts.
907 909 */
908 910 static void
909 911 apic_enable_intr(processorid_t cpun)
910 912 {
911 913 int i;
912 914 apic_irq_t *irq_ptr;
913 915 ulong_t iflag;
914 916
915 917 iflag = intr_clear();
916 918 lock_set(&apic_ioapic_lock);
917 919
918 920 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
919 921
920 922 i = apic_min_device_irq;
921 923 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
922 924 if ((irq_ptr = apic_irq_table[i]) != NULL) {
923 925 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
924 926 (void) apic_rebind_all(irq_ptr,
925 927 irq_ptr->airq_cpu);
926 928 }
927 929 }
928 930 }
929 931
930 932 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
931 933 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
932 934
933 935 lock_clear(&apic_ioapic_lock);
934 936 intr_restore(iflag);
935 937 }
936 938
937 939 /*
938 940 * If this module needs a periodic handler for the interrupt distribution, it
939 941 * can be added here. The argument to the periodic handler is not currently
940 942 * used, but is reserved for future.
941 943 */
942 944 static void
943 945 apic_post_cyclic_setup(void *arg)
944 946 {
945 947 _NOTE(ARGUNUSED(arg))
946 948
947 949 cyc_handler_t cyh;
948 950 cyc_time_t cyt;
949 951
950 952 /* cpu_lock is held */
951 953 /* set up a periodic handler for intr redistribution */
952 954
953 955 /*
954 956 * In peridoc mode intr redistribution processing is done in
955 957 * apic_intr_enter during clk intr processing
956 958 */
957 959 if (!apic_oneshot)
958 960 return;
959 961
960 962 /*
961 963 * Register a periodical handler for the redistribution processing.
962 964 * Though we would generally prefer to use the DDI interface for
963 965 * periodic handler invocation, ddi_periodic_add(9F), we are
964 966 * unfortunately already holding cpu_lock, which ddi_periodic_add will
965 967 * attempt to take for us. Thus, we add our own cyclic directly:
966 968 */
967 969 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
968 970 cyh.cyh_arg = NULL;
969 971 cyh.cyh_level = CY_LOW_LEVEL;
970 972
971 973 cyt.cyt_when = 0;
972 974 cyt.cyt_interval = apic_redistribute_sample_interval;
973 975
974 976 apic_cyclic_id = cyclic_add(&cyh, &cyt);
975 977 }
976 978
977 979 static void
978 980 apic_redistribute_compute(void)
979 981 {
980 982 int i, j, max_busy;
981 983
982 984 if (apic_enable_dynamic_migration) {
983 985 if (++apic_nticks == apic_sample_factor_redistribution) {
984 986 /*
985 987 * Time to call apic_intr_redistribute().
986 988 * reset apic_nticks. This will cause max_busy
987 989 * to be calculated below and if it is more than
988 990 * apic_int_busy, we will do the whole thing
989 991 */
990 992 apic_nticks = 0;
991 993 }
992 994 max_busy = 0;
993 995 for (i = 0; i < apic_nproc; i++) {
994 996 if (!apic_cpu_in_range(i))
995 997 continue;
996 998
997 999 /*
998 1000 * Check if curipl is non zero & if ISR is in
999 1001 * progress
1000 1002 */
1001 1003 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1002 1004 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1003 1005
1004 1006 int irq;
1005 1007 apic_cpus[i].aci_busy++;
1006 1008 irq = apic_cpus[i].aci_current[j];
1007 1009 apic_irq_table[irq]->airq_busy++;
1008 1010 }
1009 1011
1010 1012 if (!apic_nticks &&
1011 1013 (apic_cpus[i].aci_busy > max_busy))
1012 1014 max_busy = apic_cpus[i].aci_busy;
1013 1015 }
1014 1016 if (!apic_nticks) {
1015 1017 if (max_busy > apic_int_busy_mark) {
1016 1018 /*
1017 1019 * We could make the following check be
1018 1020 * skipped > 1 in which case, we get a
1019 1021 * redistribution at half the busy mark (due to
1020 1022 * double interval). Need to be able to collect
1021 1023 * more empirical data to decide if that is a
1022 1024 * good strategy. Punt for now.
1023 1025 */
1024 1026 if (apic_skipped_redistribute) {
1025 1027 apic_cleanup_busy();
1026 1028 apic_skipped_redistribute = 0;
1027 1029 } else {
1028 1030 apic_intr_redistribute();
1029 1031 }
1030 1032 } else
1031 1033 apic_skipped_redistribute++;
1032 1034 }
1033 1035 }
1034 1036 }
1035 1037
1036 1038
1037 1039 /*
1038 1040 * The following functions are in the platform specific file so that they
1039 1041 * can be different functions depending on whether we are running on
1040 1042 * bare metal or a hypervisor.
1041 1043 */
1042 1044
1043 1045 /*
1044 1046 * Check to make sure there are enough irq slots
1045 1047 */
1046 1048 int
1047 1049 apic_check_free_irqs(int count)
1048 1050 {
1049 1051 int i, avail;
1050 1052
1051 1053 avail = 0;
1052 1054 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1053 1055 if ((apic_irq_table[i] == NULL) ||
1054 1056 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1055 1057 if (++avail >= count)
1056 1058 return (PSM_SUCCESS);
1057 1059 }
1058 1060 }
1059 1061 return (PSM_FAILURE);
1060 1062 }
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1061 1063
1062 1064 /*
1063 1065 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1064 1066 */
1065 1067 int
1066 1068 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1067 1069 int behavior)
1068 1070 {
1069 1071 int rcount, i;
1070 1072 uchar_t start, irqno;
1071 - uint32_t cpu;
1073 + uint32_t cpu = 0;
1072 1074 major_t major;
1073 1075 apic_irq_t *irqptr;
1074 1076
1075 1077 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1076 1078 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1077 1079 (void *)dip, inum, pri, count, behavior));
1078 1080
1079 1081 if (count > 1) {
1080 1082 if (behavior == DDI_INTR_ALLOC_STRICT &&
1081 1083 apic_multi_msi_enable == 0)
1082 1084 return (0);
1083 1085 if (apic_multi_msi_enable == 0)
1084 1086 count = 1;
1085 1087 }
1086 1088
1087 1089 if ((rcount = apic_navail_vector(dip, pri)) > count)
1088 1090 rcount = count;
1089 1091 else if (rcount == 0 || (rcount < count &&
1090 1092 behavior == DDI_INTR_ALLOC_STRICT))
1091 1093 return (0);
1092 1094
1093 1095 /* if not ISP2, then round it down */
1094 1096 if (!ISP2(rcount))
1095 1097 rcount = 1 << (highbit(rcount) - 1);
1096 1098
1097 1099 mutex_enter(&airq_mutex);
1098 1100
1099 1101 for (start = 0; rcount > 0; rcount >>= 1) {
1100 1102 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1101 1103 behavior == DDI_INTR_ALLOC_STRICT)
1102 1104 break;
1103 1105 }
1104 1106
1105 1107 if (start == 0) {
1106 1108 /* no vector available */
1107 1109 mutex_exit(&airq_mutex);
1108 1110 return (0);
1109 1111 }
1110 1112
1111 1113 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1112 1114 /* not enough free irq slots available */
1113 1115 mutex_exit(&airq_mutex);
1114 1116 return (0);
1115 1117 }
1116 1118
1117 1119 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1118 1120 for (i = 0; i < rcount; i++) {
1119 1121 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1120 1122 (uchar_t)-1) {
1121 1123 /*
1122 1124 * shouldn't happen because of the
1123 1125 * apic_check_free_irqs() check earlier
1124 1126 */
1125 1127 mutex_exit(&airq_mutex);
1126 1128 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1127 1129 "apic_allocate_irq failed\n"));
1128 1130 return (i);
1129 1131 }
1130 1132 apic_max_device_irq = max(irqno, apic_max_device_irq);
1131 1133 apic_min_device_irq = min(irqno, apic_min_device_irq);
1132 1134 irqptr = apic_irq_table[irqno];
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1133 1135 #ifdef DEBUG
1134 1136 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1135 1137 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1136 1138 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1137 1139 #endif
1138 1140 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1139 1141
1140 1142 irqptr->airq_vector = (uchar_t)(start + i);
1141 1143 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1142 1144 irqptr->airq_intin_no = (uchar_t)rcount;
1143 - irqptr->airq_ipl = pri;
1145 + ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1146 + irqptr->airq_ipl = (uchar_t)pri;
1144 1147 irqptr->airq_vector = start + i;
1145 1148 irqptr->airq_origirq = (uchar_t)(inum + i);
1146 1149 irqptr->airq_share_id = 0;
1147 1150 irqptr->airq_mps_intr_index = MSI_INDEX;
1148 1151 irqptr->airq_dip = dip;
1149 1152 irqptr->airq_major = major;
1150 1153 if (i == 0) /* they all bound to the same cpu */
1151 1154 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1152 1155 0xff, 0xff);
1153 1156 else
1154 1157 irqptr->airq_cpu = cpu;
1155 1158 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1156 1159 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1157 1160 (void *)irqptr->airq_dip, irqptr->airq_vector,
1158 1161 irqptr->airq_origirq, pri));
1159 1162 }
1160 1163 mutex_exit(&airq_mutex);
1161 1164 return (rcount);
1162 1165 }
1163 1166
1164 1167 /*
1165 1168 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1166 1169 */
1167 1170 int
1168 1171 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1169 1172 int behavior)
1170 1173 {
1171 1174 int rcount, i;
1172 1175 major_t major;
1173 1176
1174 1177 mutex_enter(&airq_mutex);
1175 1178
1176 1179 if ((rcount = apic_navail_vector(dip, pri)) > count)
1177 1180 rcount = count;
1178 1181 else if (rcount == 0 || (rcount < count &&
1179 1182 behavior == DDI_INTR_ALLOC_STRICT)) {
1180 1183 rcount = 0;
1181 1184 goto out;
1182 1185 }
1183 1186
1184 1187 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1185 1188 /* not enough free irq slots available */
1186 1189 rcount = 0;
1187 1190 goto out;
1188 1191 }
1189 1192
1190 1193 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1191 1194 for (i = 0; i < rcount; i++) {
1192 1195 uchar_t vector, irqno;
1193 1196 apic_irq_t *irqptr;
1194 1197
1195 1198 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1196 1199 (uchar_t)-1) {
1197 1200 /*
1198 1201 * shouldn't happen because of the
1199 1202 * apic_check_free_irqs() check earlier
1200 1203 */
1201 1204 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1202 1205 "apic_allocate_irq failed\n"));
1203 1206 rcount = i;
1204 1207 goto out;
1205 1208 }
1206 1209 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1207 1210 /*
1208 1211 * shouldn't happen because of the
1209 1212 * apic_navail_vector() call earlier
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1210 1213 */
1211 1214 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1212 1215 "apic_allocate_vector failed\n"));
1213 1216 rcount = i;
1214 1217 goto out;
1215 1218 }
1216 1219 apic_max_device_irq = max(irqno, apic_max_device_irq);
1217 1220 apic_min_device_irq = min(irqno, apic_min_device_irq);
1218 1221 irqptr = apic_irq_table[irqno];
1219 1222 irqptr->airq_vector = (uchar_t)vector;
1220 - irqptr->airq_ipl = pri;
1223 + ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1224 + irqptr->airq_ipl = (uchar_t)pri;
1221 1225 irqptr->airq_origirq = (uchar_t)(inum + i);
1222 1226 irqptr->airq_share_id = 0;
1223 1227 irqptr->airq_mps_intr_index = MSIX_INDEX;
1224 1228 irqptr->airq_dip = dip;
1225 1229 irqptr->airq_major = major;
1226 1230 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1227 1231 }
1228 1232 out:
1229 1233 mutex_exit(&airq_mutex);
1230 1234 return (rcount);
1231 1235 }
1232 1236
1233 1237 /*
1234 1238 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1235 1239 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1236 1240 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1237 1241 * requests and allocated only when pri is set.
1238 1242 */
1239 1243 uchar_t
1240 1244 apic_allocate_vector(int ipl, int irq, int pri)
1241 1245 {
1242 1246 int lowest, highest, i;
1243 1247
1244 1248 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1245 1249 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1246 1250
1247 1251 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1248 1252 lowest -= APIC_VECTOR_PER_IPL;
1249 1253
1250 1254 #ifdef DEBUG
1251 1255 if (apic_restrict_vector) /* for testing shared interrupt logic */
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1252 1256 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1253 1257 #endif /* DEBUG */
1254 1258 if (pri == 0)
1255 1259 highest -= APIC_HI_PRI_VECTS;
1256 1260
1257 1261 for (i = lowest; i <= highest; i++) {
1258 1262 if (APIC_CHECK_RESERVE_VECTORS(i))
1259 1263 continue;
1260 1264 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1261 1265 apic_vector_to_irq[i] = (uchar_t)irq;
1262 - return (i);
1266 + ASSERT(i >= 0 && i <= UCHAR_MAX);
1267 + return ((uchar_t)i);
1263 1268 }
1264 1269 }
1265 1270
1266 1271 return (0);
1267 1272 }
1268 1273
1269 1274 /* Mark vector as not being used by any irq */
1270 1275 void
1271 1276 apic_free_vector(uchar_t vector)
1272 1277 {
1273 1278 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1274 1279 }
1275 1280
1276 1281 /*
1277 1282 * Call rebind to do the actual programming.
1278 1283 * Must be called with interrupts disabled and apic_ioapic_lock held
1279 1284 * 'p' is polymorphic -- if this function is called to process a deferred
1280 1285 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1281 1286 * the irq pointer is retrieved. If not doing deferred reprogramming,
1282 1287 * p is of the type 'apic_irq_t *'.
1283 1288 *
1284 1289 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1285 1290 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1286 1291 * taken offline after a cpu is selected, but before apic_rebind is called to
1287 1292 * bind interrupts to it.
1288 1293 */
1289 1294 int
1290 1295 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1291 1296 {
1292 1297 apic_irq_t *irqptr;
1293 1298 struct ioapic_reprogram_data *drep = NULL;
1294 1299 int rv;
1295 1300
1296 1301 if (deferred) {
1297 1302 drep = (struct ioapic_reprogram_data *)p;
1298 1303 ASSERT(drep != NULL);
1299 1304 irqptr = drep->irqp;
1300 1305 } else
1301 1306 irqptr = (apic_irq_t *)p;
1302 1307
1303 1308 ASSERT(irqptr != NULL);
1304 1309
1305 1310 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1306 1311 if (rv) {
1307 1312 /*
1308 1313 * CPU is not up or interrupts are disabled. Fall back to
1309 1314 * the first available CPU
1310 1315 */
1311 1316 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1312 1317 drep);
1313 1318 }
1314 1319
1315 1320 return (rv);
1316 1321 }
1317 1322
1318 1323
1319 1324 uchar_t
1320 1325 apic_modify_vector(uchar_t vector, int irq)
1321 1326 {
1322 1327 apic_vector_to_irq[vector] = (uchar_t)irq;
1323 1328 return (vector);
1324 1329 }
1325 1330
1326 1331 char *
1327 1332 apic_get_apic_type(void)
1328 1333 {
1329 1334 return (apic_psm_info.p_mach_idstring);
1330 1335 }
1331 1336
1332 1337 void
1333 1338 x2apic_update_psm(void)
1334 1339 {
1335 1340 struct psm_ops *pops = &apic_ops;
1336 1341
1337 1342 ASSERT(pops != NULL);
1338 1343
1339 1344 pops->psm_intr_exit = x2apic_intr_exit;
1340 1345 pops->psm_setspl = x2apic_setspl;
1341 1346
1342 1347 pops->psm_send_ipi = x2apic_send_ipi;
1343 1348 send_dirintf = pops->psm_send_ipi;
1344 1349
1345 1350 apic_mode = LOCAL_X2APIC;
1346 1351 apic_change_ops();
1347 1352 }
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