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8626 make pcplusmp and apix warning-free
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic_introp.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic_introp.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2013 Pluribus Networks, Inc.
24 + * Copyright 2017 Joyent, Inc.
24 25 */
25 26
26 27 /*
27 28 * apic_introp.c:
28 29 * Has code for Advanced DDI interrupt framework support.
29 30 */
30 31
31 32 #include <sys/cpuvar.h>
32 33 #include <sys/psm.h>
33 34 #include <sys/archsystm.h>
34 35 #include <sys/apic.h>
35 36 #include <sys/sunddi.h>
36 37 #include <sys/ddi_impldefs.h>
37 38 #include <sys/mach_intr.h>
38 39 #include <sys/sysmacros.h>
39 40 #include <sys/trap.h>
40 41 #include <sys/pci.h>
41 42 #include <sys/pci_intr_lib.h>
42 43 #include <sys/apic_common.h>
43 44
45 +#define UCHAR_MAX UINT8_MAX
46 +
44 47 extern struct av_head autovect[];
45 48
46 49 /*
47 50 * Local Function Prototypes
48 51 */
49 52 apic_irq_t *apic_find_irq(dev_info_t *, struct intrspec *, int);
50 53
51 54 /*
52 55 * apic_pci_msi_enable_vector:
53 56 * Set the address/data fields in the MSI/X capability structure
54 57 * XXX: MSI-X support
55 58 */
56 59 /* ARGSUSED */
57 60 void
58 61 apic_pci_msi_enable_vector(apic_irq_t *irq_ptr, int type, int inum, int vector,
59 62 int count, int target_apic_id)
60 63 {
61 64 uint64_t msi_addr, msi_data;
62 65 ushort_t msi_ctrl;
63 66 dev_info_t *dip = irq_ptr->airq_dip;
64 67 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
65 68 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(dip);
66 69 msi_regs_t msi_regs;
67 70 int irqno, i;
68 71 void *intrmap_tbl[PCI_MSI_MAX_INTRS];
69 72
70 73 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: dip=0x%p\n"
71 74 "\tdriver = %s, inum=0x%x vector=0x%x apicid=0x%x\n", (void *)dip,
72 75 ddi_driver_name(dip), inum, vector, target_apic_id));
73 76
74 77 ASSERT((handle != NULL) && (cap_ptr != 0));
75 78
76 79 msi_regs.mr_data = vector;
77 80 msi_regs.mr_addr = target_apic_id;
78 81
79 82 for (i = 0; i < count; i++) {
80 83 irqno = apic_vector_to_irq[vector + i];
81 84 intrmap_tbl[i] = apic_irq_table[irqno]->airq_intrmap_private;
82 85 }
83 86 apic_vt_ops->apic_intrmap_alloc_entry(intrmap_tbl, dip, type,
84 87 count, 0xff);
85 88 for (i = 0; i < count; i++) {
86 89 irqno = apic_vector_to_irq[vector + i];
87 90 apic_irq_table[irqno]->airq_intrmap_private =
88 91 intrmap_tbl[i];
89 92 }
90 93
91 94 apic_vt_ops->apic_intrmap_map_entry(irq_ptr->airq_intrmap_private,
92 95 (void *)&msi_regs, type, count);
93 96 apic_vt_ops->apic_intrmap_record_msi(irq_ptr->airq_intrmap_private,
94 97 &msi_regs);
95 98
96 99 /* MSI Address */
97 100 msi_addr = msi_regs.mr_addr;
98 101
99 102 /* MSI Data: MSI is edge triggered according to spec */
100 103 msi_data = msi_regs.mr_data;
101 104
102 105 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: addr=0x%lx "
103 106 "data=0x%lx\n", (long)msi_addr, (long)msi_data));
104 107
105 108 if (type == DDI_INTR_TYPE_MSI) {
106 109 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
107 110
108 111 /* Set the bits to inform how many MSIs are enabled */
109 112 msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT);
110 113 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
111 114
112 115 /*
113 116 * Only set vector if not on hypervisor
114 117 */
115 118 pci_config_put32(handle,
116 119 cap_ptr + PCI_MSI_ADDR_OFFSET, msi_addr);
117 120
118 121 if (msi_ctrl & PCI_MSI_64BIT_MASK) {
119 122 pci_config_put32(handle,
120 123 cap_ptr + PCI_MSI_ADDR_OFFSET + 4, msi_addr >> 32);
121 124 pci_config_put16(handle,
122 125 cap_ptr + PCI_MSI_64BIT_DATA, msi_data);
123 126 } else {
124 127 pci_config_put16(handle,
125 128 cap_ptr + PCI_MSI_32BIT_DATA, msi_data);
126 129 }
127 130
128 131 } else if (type == DDI_INTR_TYPE_MSIX) {
129 132 uintptr_t off;
130 133 ddi_intr_msix_t *msix_p = i_ddi_get_msix(dip);
131 134
132 135 ASSERT(msix_p != NULL);
133 136
134 137 /* Offset into the "inum"th entry in the MSI-X table */
135 138 off = (uintptr_t)msix_p->msix_tbl_addr +
136 139 (inum * PCI_MSIX_VECTOR_SIZE);
137 140
138 141 ddi_put32(msix_p->msix_tbl_hdl,
139 142 (uint32_t *)(off + PCI_MSIX_DATA_OFFSET), msi_data);
140 143 ddi_put32(msix_p->msix_tbl_hdl,
141 144 (uint32_t *)(off + PCI_MSIX_LOWER_ADDR_OFFSET), msi_addr);
142 145 ddi_put32(msix_p->msix_tbl_hdl,
143 146 (uint32_t *)(off + PCI_MSIX_UPPER_ADDR_OFFSET),
144 147 msi_addr >> 32);
145 148 }
146 149 }
147 150
148 151 /*
149 152 * This function returns the no. of vectors available for the pri.
150 153 * dip is not used at this moment. If we really don't need that,
151 154 * it will be removed.
152 155 */
153 156 /*ARGSUSED*/
154 157 int
155 158 apic_navail_vector(dev_info_t *dip, int pri)
156 159 {
157 160 int lowest, highest, i, navail, count;
158 161
159 162 DDI_INTR_IMPLDBG((CE_CONT, "apic_navail_vector: dip: %p, pri: %x\n",
160 163 (void *)dip, pri));
161 164
162 165 highest = apic_ipltopri[pri] + APIC_VECTOR_MASK;
163 166 lowest = apic_ipltopri[pri - 1] + APIC_VECTOR_PER_IPL;
164 167 navail = count = 0;
165 168
166 169 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
167 170 lowest -= APIC_VECTOR_PER_IPL;
168 171
169 172 /* It has to be contiguous */
170 173 for (i = lowest; i <= highest; i++) {
171 174 count = 0;
172 175 while ((apic_vector_to_irq[i] == APIC_RESV_IRQ) &&
173 176 (i <= highest)) {
174 177 if (APIC_CHECK_RESERVE_VECTORS(i))
175 178 break;
176 179 count++;
177 180 i++;
178 181 }
179 182 if (count > navail)
180 183 navail = count;
181 184 }
182 185 return (navail);
183 186 }
184 187
185 188 /*
186 189 * Finds "count" contiguous MSI vectors starting at the proper alignment
187 190 * at "pri".
188 191 * Caller needs to make sure that count has to be power of 2 and should not
189 192 * be < 1.
190 193 */
191 194 uchar_t
192 195 apic_find_multi_vectors(int pri, int count)
193 196 {
194 197 int lowest, highest, i, navail, start, msibits;
195 198
196 199 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_mult: pri: %x, count: %x\n",
197 200 pri, count));
198 201
199 202 highest = apic_ipltopri[pri] + APIC_VECTOR_MASK;
200 203 lowest = apic_ipltopri[pri - 1] + APIC_VECTOR_PER_IPL;
201 204 navail = 0;
202 205
203 206 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
204 207 lowest -= APIC_VECTOR_PER_IPL;
205 208
206 209 /*
207 210 * msibits is the no. of lower order message data bits for the
208 211 * allocated MSI vectors and is used to calculate the aligned
209 212 * starting vector
210 213 */
211 214 msibits = count - 1;
212 215
213 216 /* It has to be contiguous */
214 217 for (i = lowest; i <= highest; i++) {
215 218 navail = 0;
216 219
217 220 /*
218 221 * starting vector has to be aligned accordingly for
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219 222 * multiple MSIs
220 223 */
221 224 if (msibits)
222 225 i = (i + msibits) & ~msibits;
223 226 start = i;
224 227 while ((apic_vector_to_irq[i] == APIC_RESV_IRQ) &&
225 228 (i <= highest)) {
226 229 if (APIC_CHECK_RESERVE_VECTORS(i))
227 230 break;
228 231 navail++;
229 - if (navail >= count)
230 - return (start);
232 + if (navail >= count) {
233 + ASSERT(start >= 0 && start <= UCHAR_MAX);
234 + return ((uchar_t)start);
235 + }
231 236 i++;
232 237 }
233 238 }
234 239 return (0);
235 240 }
236 241
237 242
238 243 /*
239 244 * It finds the apic_irq_t associates with the dip, ispec and type.
240 245 */
241 246 apic_irq_t *
242 247 apic_find_irq(dev_info_t *dip, struct intrspec *ispec, int type)
243 248 {
244 249 apic_irq_t *irqp;
245 250 int i;
246 251
247 252 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: dip=0x%p vec=0x%x "
248 253 "ipl=0x%x type=0x%x\n", (void *)dip, ispec->intrspec_vec,
249 254 ispec->intrspec_pri, type));
250 255
251 256 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
252 257 for (irqp = apic_irq_table[i]; irqp; irqp = irqp->airq_next) {
253 258 if ((irqp->airq_dip == dip) &&
254 259 (irqp->airq_origirq == ispec->intrspec_vec) &&
255 260 (irqp->airq_ipl == ispec->intrspec_pri)) {
256 261 if (type == DDI_INTR_TYPE_MSI) {
257 262 if (irqp->airq_mps_intr_index ==
258 263 MSI_INDEX)
259 264 return (irqp);
260 265 } else if (type == DDI_INTR_TYPE_MSIX) {
261 266 if (irqp->airq_mps_intr_index ==
262 267 MSIX_INDEX)
263 268 return (irqp);
264 269 } else
265 270 return (irqp);
266 271 }
267 272 }
268 273 }
269 274 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: return NULL\n"));
270 275 return (NULL);
271 276 }
272 277
273 278 /*
274 279 * This function will return the pending bit of the irqp.
275 280 * It either comes from the IRR register of the APIC or the RDT
276 281 * entry of the I/O APIC.
277 282 * For the IRR to work, it needs to be to its binding CPU
278 283 */
279 284 static int
280 285 apic_get_pending(apic_irq_t *irqp, int type)
281 286 {
282 287 int bit, index, irr, pending;
283 288 int intin_no;
284 289 int apic_ix;
285 290
286 291 DDI_INTR_IMPLDBG((CE_CONT, "apic_get_pending: irqp: %p, cpuid: %x "
287 292 "type: %x\n", (void *)irqp, irqp->airq_cpu & ~IRQ_USER_BOUND,
288 293 type));
289 294
290 295 /* need to get on the bound cpu */
291 296 mutex_enter(&cpu_lock);
292 297 affinity_set(irqp->airq_cpu & ~IRQ_USER_BOUND);
293 298
294 299 index = irqp->airq_vector / 32;
295 300 bit = irqp->airq_vector % 32;
296 301 irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
297 302
298 303 affinity_clear();
299 304 mutex_exit(&cpu_lock);
300 305
301 306 pending = (irr & (1 << bit)) ? 1 : 0;
302 307 if (!pending && (type == DDI_INTR_TYPE_FIXED)) {
303 308 /* check I/O APIC for fixed interrupt */
304 309 intin_no = irqp->airq_intin_no;
305 310 apic_ix = irqp->airq_ioapicindex;
306 311 pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_no) &
307 312 AV_PENDING) ? 1 : 0;
308 313 }
309 314 return (pending);
310 315 }
311 316
312 317
313 318 /*
314 319 * This function will clear the mask for the interrupt on the I/O APIC
315 320 */
316 321 static void
317 322 apic_clear_mask(apic_irq_t *irqp)
318 323 {
319 324 int intin_no;
320 325 ulong_t iflag;
321 326 int32_t rdt_entry;
322 327 int apic_ix;
323 328
324 329 DDI_INTR_IMPLDBG((CE_CONT, "apic_clear_mask: irqp: %p\n",
325 330 (void *)irqp));
326 331
327 332 intin_no = irqp->airq_intin_no;
328 333 apic_ix = irqp->airq_ioapicindex;
329 334
330 335 iflag = intr_clear();
331 336 lock_set(&apic_ioapic_lock);
332 337
333 338 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_no);
334 339
335 340 /* clear mask */
336 341 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_no,
337 342 ((~AV_MASK) & rdt_entry));
338 343
339 344 lock_clear(&apic_ioapic_lock);
340 345 intr_restore(iflag);
341 346 }
342 347
343 348
344 349 /*
345 350 * This function will mask the interrupt on the I/O APIC
346 351 */
347 352 static void
348 353 apic_set_mask(apic_irq_t *irqp)
349 354 {
350 355 int intin_no;
351 356 int apic_ix;
352 357 ulong_t iflag;
353 358 int32_t rdt_entry;
354 359
355 360 DDI_INTR_IMPLDBG((CE_CONT, "apic_set_mask: irqp: %p\n", (void *)irqp));
356 361
357 362 intin_no = irqp->airq_intin_no;
358 363 apic_ix = irqp->airq_ioapicindex;
359 364
360 365 iflag = intr_clear();
361 366
362 367 lock_set(&apic_ioapic_lock);
363 368
364 369 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_no);
365 370
366 371 /* mask it */
367 372 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_no,
368 373 (AV_MASK | rdt_entry));
369 374
370 375 lock_clear(&apic_ioapic_lock);
371 376 intr_restore(iflag);
372 377 }
373 378
374 379
375 380 void
376 381 apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, int type)
377 382 {
378 383 int i;
379 384 apic_irq_t *irqptr;
380 385 struct intrspec ispec;
381 386
382 387 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: dip: %p inum: %x "
383 388 "count: %x pri: %x type: %x\n",
384 389 (void *)dip, inum, count, pri, type));
385 390
386 391 /* for MSI/X only */
387 392 if (!DDI_INTR_IS_MSI_OR_MSIX(type))
388 393 return;
389 394
390 395 for (i = 0; i < count; i++) {
391 396 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: inum=0x%x "
392 397 "pri=0x%x count=0x%x\n", inum, pri, count));
393 398 ispec.intrspec_vec = inum + i;
394 399 ispec.intrspec_pri = pri;
395 400 if ((irqptr = apic_find_irq(dip, &ispec, type)) == NULL) {
396 401 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: "
397 402 "dip=0x%p inum=0x%x pri=0x%x apic_find_irq() "
398 403 "failed\n", (void *)dip, inum, pri));
399 404 continue;
400 405 }
401 406 irqptr->airq_mps_intr_index = FREE_INDEX;
402 407 apic_vector_to_irq[irqptr->airq_vector] = APIC_RESV_IRQ;
403 408 }
404 409 }
405 410
406 411 /*
407 412 * apic_pci_msi_enable_mode:
408 413 */
409 414 void
410 415 apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum)
411 416 {
412 417 ushort_t msi_ctrl;
413 418 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(rdip);
414 419 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(rdip);
415 420
416 421 ASSERT((handle != NULL) && (cap_ptr != 0));
417 422
418 423 if (type == DDI_INTR_TYPE_MSI) {
419 424 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
420 425 if ((msi_ctrl & PCI_MSI_ENABLE_BIT))
421 426 return;
422 427
423 428 msi_ctrl |= PCI_MSI_ENABLE_BIT;
424 429 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
425 430
426 431 } else if (type == DDI_INTR_TYPE_MSIX) {
427 432 uintptr_t off;
428 433 uint32_t mask;
429 434 ddi_intr_msix_t *msix_p;
430 435
431 436 msix_p = i_ddi_get_msix(rdip);
432 437
433 438 ASSERT(msix_p != NULL);
434 439
435 440 /* Offset into "inum"th entry in the MSI-X table & clear mask */
436 441 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
437 442 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
438 443
439 444 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
440 445
441 446 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, (mask & ~1));
442 447
443 448 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
444 449
445 450 if (!(msi_ctrl & PCI_MSIX_ENABLE_BIT)) {
446 451 msi_ctrl |= PCI_MSIX_ENABLE_BIT;
447 452 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL,
448 453 msi_ctrl);
449 454 }
450 455 }
451 456 }
452 457
453 458 static int
454 459 apic_set_cpu(int irqno, int cpu, int *result)
455 460 {
456 461 apic_irq_t *irqp;
457 462 ulong_t iflag;
458 463 int ret;
459 464
460 465 DDI_INTR_IMPLDBG((CE_CONT, "APIC_SET_CPU\n"));
461 466
462 467 mutex_enter(&airq_mutex);
463 468 irqp = apic_irq_table[irqno];
464 469 mutex_exit(&airq_mutex);
465 470
466 471 if (irqp == NULL) {
467 472 *result = ENXIO;
468 473 return (PSM_FAILURE);
469 474 }
470 475
471 476 /* Fail if this is an MSI intr and is part of a group. */
472 477 if ((irqp->airq_mps_intr_index == MSI_INDEX) &&
473 478 (irqp->airq_intin_no > 1)) {
474 479 *result = ENXIO;
475 480 return (PSM_FAILURE);
476 481 }
477 482
478 483 iflag = intr_clear();
479 484 lock_set(&apic_ioapic_lock);
480 485
481 486 ret = apic_rebind_all(irqp, cpu);
482 487
483 488 lock_clear(&apic_ioapic_lock);
484 489 intr_restore(iflag);
485 490
486 491 if (ret) {
487 492 *result = EIO;
488 493 return (PSM_FAILURE);
489 494 }
490 495 /*
491 496 * keep tracking the default interrupt cpu binding
492 497 */
493 498 irqp->airq_cpu = cpu;
494 499
495 500 *result = 0;
496 501 return (PSM_SUCCESS);
497 502 }
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498 503
499 504 static int
500 505 apic_grp_set_cpu(int irqno, int new_cpu, int *result)
501 506 {
502 507 dev_info_t *orig_dip;
503 508 uint32_t orig_cpu;
504 509 ulong_t iflag;
505 510 apic_irq_t *irqps[PCI_MSI_MAX_INTRS];
506 511 int i;
507 512 int cap_ptr;
508 - int msi_mask_off;
513 + int msi_mask_off = 0;
509 514 ushort_t msi_ctrl;
510 - uint32_t msi_pvm;
515 + uint32_t msi_pvm = 0;
511 516 ddi_acc_handle_t handle;
512 517 int num_vectors = 0;
513 518 uint32_t vector;
514 519
515 520 DDI_INTR_IMPLDBG((CE_CONT, "APIC_GRP_SET_CPU\n"));
516 521
517 522 /*
518 523 * Take mutex to insure that table doesn't change out from underneath
519 524 * us while we're playing with it.
520 525 */
521 526 mutex_enter(&airq_mutex);
522 527 irqps[0] = apic_irq_table[irqno];
523 528 orig_cpu = irqps[0]->airq_temp_cpu;
524 529 orig_dip = irqps[0]->airq_dip;
525 530 num_vectors = irqps[0]->airq_intin_no;
526 531 vector = irqps[0]->airq_vector;
527 532
528 533 /* A "group" of 1 */
529 534 if (num_vectors == 1) {
530 535 mutex_exit(&airq_mutex);
531 536 return (apic_set_cpu(irqno, new_cpu, result));
532 537 }
533 538
534 539 *result = ENXIO;
535 540
536 541 if (irqps[0]->airq_mps_intr_index != MSI_INDEX) {
537 542 mutex_exit(&airq_mutex);
538 543 DDI_INTR_IMPLDBG((CE_CONT, "set_grp: intr not MSI\n"));
539 544 goto set_grp_intr_done;
540 545 }
541 546 if ((num_vectors < 1) || ((num_vectors - 1) & vector)) {
542 547 mutex_exit(&airq_mutex);
543 548 DDI_INTR_IMPLDBG((CE_CONT,
544 549 "set_grp: base vec not part of a grp or not aligned: "
545 550 "vec:0x%x, num_vec:0x%x\n", vector, num_vectors));
546 551 goto set_grp_intr_done;
547 552 }
548 553 DDI_INTR_IMPLDBG((CE_CONT, "set_grp: num intrs in grp: %d\n",
549 554 num_vectors));
550 555
551 556 ASSERT((num_vectors + vector) < APIC_MAX_VECTOR);
552 557
553 558 *result = EIO;
554 559
555 560 /*
556 561 * All IRQ entries in the table for the given device will be not
557 562 * shared. Since they are not shared, the dip in the table will
558 563 * be true to the device of interest.
559 564 */
560 565 for (i = 1; i < num_vectors; i++) {
561 566 irqps[i] = apic_irq_table[apic_vector_to_irq[vector + i]];
562 567 if (irqps[i] == NULL) {
563 568 mutex_exit(&airq_mutex);
564 569 goto set_grp_intr_done;
565 570 }
566 571 #ifdef DEBUG
567 572 /* Sanity check: CPU and dip is the same for all entries. */
568 573 if ((irqps[i]->airq_dip != orig_dip) ||
569 574 (irqps[i]->airq_temp_cpu != orig_cpu)) {
570 575 mutex_exit(&airq_mutex);
571 576 DDI_INTR_IMPLDBG((CE_CONT,
572 577 "set_grp: cpu or dip for vec 0x%x difft than for "
573 578 "vec 0x%x\n", vector, vector + i));
574 579 DDI_INTR_IMPLDBG((CE_CONT,
575 580 " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
576 581 irqps[i]->airq_temp_cpu, (void *)orig_dip,
577 582 (void *)irqps[i]->airq_dip));
578 583 goto set_grp_intr_done;
579 584 }
580 585 #endif /* DEBUG */
581 586 }
582 587 mutex_exit(&airq_mutex);
583 588
584 589 cap_ptr = i_ddi_get_msi_msix_cap_ptr(orig_dip);
585 590 handle = i_ddi_get_pci_config_handle(orig_dip);
586 591 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
587 592
588 593 /* MSI Per vector masking is supported. */
589 594 if (msi_ctrl & PCI_MSI_PVM_MASK) {
590 595 if (msi_ctrl & PCI_MSI_64BIT_MASK)
591 596 msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
592 597 else
593 598 msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
594 599 msi_pvm = pci_config_get32(handle, msi_mask_off);
595 600 pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
596 601 DDI_INTR_IMPLDBG((CE_CONT,
597 602 "set_grp: pvm supported. Mask set to 0x%x\n",
598 603 pci_config_get32(handle, msi_mask_off)));
599 604 }
600 605
601 606 iflag = intr_clear();
602 607 lock_set(&apic_ioapic_lock);
603 608
604 609 /*
605 610 * Do the first rebind and check for errors. Apic_rebind_all returns
606 611 * an error if the CPU is not accepting interrupts. If the first one
607 612 * succeeds they all will.
608 613 */
609 614 if (apic_rebind_all(irqps[0], new_cpu))
610 615 (void) apic_rebind_all(irqps[0], orig_cpu);
611 616 else {
612 617 irqps[0]->airq_cpu = new_cpu;
613 618
614 619 for (i = 1; i < num_vectors; i++) {
615 620 (void) apic_rebind_all(irqps[i], new_cpu);
616 621 irqps[i]->airq_cpu = new_cpu;
617 622 }
618 623 *result = 0; /* SUCCESS */
619 624 }
620 625
621 626 lock_clear(&apic_ioapic_lock);
622 627 intr_restore(iflag);
623 628
624 629 /* Reenable vectors if per vector masking is supported. */
625 630 if (msi_ctrl & PCI_MSI_PVM_MASK) {
626 631 pci_config_put32(handle, msi_mask_off, msi_pvm);
627 632 DDI_INTR_IMPLDBG((CE_CONT,
628 633 "set_grp: pvm supported. Mask restored to 0x%x\n",
629 634 pci_config_get32(handle, msi_mask_off)));
630 635 }
631 636
632 637 set_grp_intr_done:
633 638 if (*result != 0)
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634 639 return (PSM_FAILURE);
635 640
636 641 return (PSM_SUCCESS);
637 642 }
638 643
639 644 int
640 645 apic_get_vector_intr_info(int vecirq, apic_get_intr_t *intr_params_p)
641 646 {
642 647 struct autovec *av_dev;
643 648 uchar_t irqno;
644 - int i;
649 + uint i;
645 650 apic_irq_t *irq_p;
646 651
647 652 /* Sanity check the vector/irq argument. */
648 653 ASSERT((vecirq >= 0) || (vecirq <= APIC_MAX_VECTOR));
649 654
650 655 mutex_enter(&airq_mutex);
651 656
652 657 /*
653 658 * Convert the vecirq arg to an irq using vector_to_irq table
654 659 * if the arg is a vector. Pass thru if already an irq.
655 660 */
656 661 if ((intr_params_p->avgi_req_flags & PSMGI_INTRBY_FLAGS) ==
657 662 PSMGI_INTRBY_VEC)
658 663 irqno = apic_vector_to_irq[vecirq];
659 664 else
660 - irqno = vecirq;
665 + irqno = (uchar_t)vecirq;
661 666
662 667 irq_p = apic_irq_table[irqno];
663 668
664 669 if ((irq_p == NULL) ||
665 670 ((irq_p->airq_mps_intr_index != RESERVE_INDEX) &&
666 671 ((irq_p->airq_temp_cpu == IRQ_UNBOUND) ||
667 672 (irq_p->airq_temp_cpu == IRQ_UNINIT)))) {
668 673 mutex_exit(&airq_mutex);
669 674 return (PSM_FAILURE);
670 675 }
671 676
672 677 if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
673 678
674 679 /* Get the (temp) cpu from apic_irq table, indexed by irq. */
675 680 intr_params_p->avgi_cpu_id = irq_p->airq_temp_cpu;
676 681
677 682 /* Return user bound info for intrd. */
678 683 if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
679 684 intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
680 685 intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
681 686 }
682 687 }
683 688
684 689 if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
685 690 intr_params_p->avgi_vector = irq_p->airq_vector;
686 691
687 692 if (intr_params_p->avgi_req_flags &
688 693 (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
689 694 /* Get number of devices from apic_irq table shared field. */
690 695 intr_params_p->avgi_num_devs = irq_p->airq_share;
691 696
692 697 if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) {
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693 698
694 699 intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS;
695 700
696 701 /* Some devices have NULL dip. Don't count these. */
697 702 if (intr_params_p->avgi_num_devs > 0) {
698 703 for (i = 0, av_dev = autovect[irqno].avh_link;
699 704 av_dev; av_dev = av_dev->av_link)
700 705 if (av_dev->av_vector && av_dev->av_dip)
701 706 i++;
702 707 intr_params_p->avgi_num_devs =
703 - MIN(intr_params_p->avgi_num_devs, i);
708 + (uchar_t)MIN(intr_params_p->avgi_num_devs, i);
704 709 }
705 710
706 711 /* There are no viable dips to return. */
707 712 if (intr_params_p->avgi_num_devs == 0)
708 713 intr_params_p->avgi_dip_list = NULL;
709 714
710 715 else { /* Return list of dips */
711 716
712 717 /* Allocate space in array for that number of devs. */
713 718 intr_params_p->avgi_dip_list = kmem_zalloc(
714 719 intr_params_p->avgi_num_devs *
715 720 sizeof (dev_info_t *),
716 721 KM_SLEEP);
717 722
718 723 /*
719 724 * Loop through the device list of the autovec table
720 725 * filling in the dip array.
721 726 *
722 727 * Note that the autovect table may have some special
723 728 * entries which contain NULL dips. These will be
724 729 * ignored.
725 730 */
726 731 for (i = 0, av_dev = autovect[irqno].avh_link;
727 732 av_dev; av_dev = av_dev->av_link)
728 733 if (av_dev->av_vector && av_dev->av_dip)
729 734 intr_params_p->avgi_dip_list[i++] =
730 735 av_dev->av_dip;
731 736 }
732 737 }
733 738
734 739 mutex_exit(&airq_mutex);
735 740
736 741 return (PSM_SUCCESS);
737 742 }
738 743
739 744 /*
740 745 * This function provides external interface to the nexus for all
741 746 * functionalities related to the new DDI interrupt framework.
742 747 *
743 748 * Input:
744 749 * dip - pointer to the dev_info structure of the requested device
745 750 * hdlp - pointer to the internal interrupt handle structure for the
746 751 * requested interrupt
747 752 * intr_op - opcode for this call
748 753 * result - pointer to the integer that will hold the result to be
749 754 * passed back if return value is PSM_SUCCESS
750 755 *
751 756 * Output:
752 757 * return value is either PSM_SUCCESS or PSM_FAILURE
753 758 */
754 759 int
755 760 apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
756 761 psm_intr_op_t intr_op, int *result)
757 762 {
758 763 int cap;
759 764 int count_vec;
760 765 int old_priority;
761 766 int new_priority;
762 767 int new_cpu;
763 768 apic_irq_t *irqp;
764 769 struct intrspec *ispec, intr_spec;
765 770
766 771 DDI_INTR_IMPLDBG((CE_CONT, "apic_intr_ops: dip: %p hdlp: %p "
767 772 "intr_op: %x\n", (void *)dip, (void *)hdlp, intr_op));
768 773
769 774 ispec = &intr_spec;
770 775 ispec->intrspec_pri = hdlp->ih_pri;
771 776 ispec->intrspec_vec = hdlp->ih_inum;
772 777 ispec->intrspec_func = hdlp->ih_cb_func;
773 778
774 779 switch (intr_op) {
775 780 case PSM_INTR_OP_CHECK_MSI:
776 781 /*
777 782 * Check MSI/X is supported or not at APIC level and
778 783 * masked off the MSI/X bits in hdlp->ih_type if not
779 784 * supported before return. If MSI/X is supported,
780 785 * leave the ih_type unchanged and return.
781 786 *
782 787 * hdlp->ih_type passed in from the nexus has all the
783 788 * interrupt types supported by the device.
784 789 */
785 790 if (apic_support_msi == 0) {
786 791 /*
787 792 * if apic_support_msi is not set, call
788 793 * apic_check_msi_support() to check whether msi
789 794 * is supported first
790 795 */
791 796 if (apic_check_msi_support() == PSM_SUCCESS)
792 797 apic_support_msi = 1;
793 798 else
794 799 apic_support_msi = -1;
795 800 }
796 801 if (apic_support_msi == 1) {
797 802 if (apic_msix_enable)
798 803 *result = hdlp->ih_type;
799 804 else
800 805 *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
801 806 } else
802 807 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
803 808 DDI_INTR_TYPE_MSIX);
804 809 break;
805 810 case PSM_INTR_OP_ALLOC_VECTORS:
806 811 if (hdlp->ih_type == DDI_INTR_TYPE_MSI)
807 812 *result = apic_alloc_msi_vectors(dip, hdlp->ih_inum,
808 813 hdlp->ih_scratch1, hdlp->ih_pri,
809 814 (int)(uintptr_t)hdlp->ih_scratch2);
810 815 else
811 816 *result = apic_alloc_msix_vectors(dip, hdlp->ih_inum,
812 817 hdlp->ih_scratch1, hdlp->ih_pri,
813 818 (int)(uintptr_t)hdlp->ih_scratch2);
814 819 break;
815 820 case PSM_INTR_OP_FREE_VECTORS:
816 821 apic_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
817 822 hdlp->ih_pri, hdlp->ih_type);
818 823 break;
819 824 case PSM_INTR_OP_NAVAIL_VECTORS:
820 825 *result = apic_navail_vector(dip, hdlp->ih_pri);
821 826 break;
822 827 case PSM_INTR_OP_XLATE_VECTOR:
823 828 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
824 829 *result = apic_introp_xlate(dip, ispec, hdlp->ih_type);
825 830 if (*result == -1)
826 831 return (PSM_FAILURE);
827 832 break;
828 833 case PSM_INTR_OP_GET_PENDING:
829 834 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL)
830 835 return (PSM_FAILURE);
831 836 *result = apic_get_pending(irqp, hdlp->ih_type);
832 837 break;
833 838 case PSM_INTR_OP_CLEAR_MASK:
834 839 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
835 840 return (PSM_FAILURE);
836 841 irqp = apic_find_irq(dip, ispec, hdlp->ih_type);
837 842 if (irqp == NULL)
838 843 return (PSM_FAILURE);
839 844 apic_clear_mask(irqp);
840 845 break;
841 846 case PSM_INTR_OP_SET_MASK:
842 847 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
843 848 return (PSM_FAILURE);
844 849 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL)
845 850 return (PSM_FAILURE);
846 851 apic_set_mask(irqp);
847 852 break;
848 853 case PSM_INTR_OP_GET_CAP:
849 854 cap = DDI_INTR_FLAG_PENDING;
850 855 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
851 856 cap |= DDI_INTR_FLAG_MASKABLE;
852 857 *result = cap;
853 858 break;
854 859 case PSM_INTR_OP_GET_SHARED:
855 860 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
856 861 return (PSM_FAILURE);
857 862 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
858 863 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL)
859 864 return (PSM_FAILURE);
860 865 *result = (irqp->airq_share > 1) ? 1: 0;
861 866 break;
862 867 case PSM_INTR_OP_SET_PRI:
863 868 old_priority = hdlp->ih_pri; /* save old value */
864 869 new_priority = *(int *)result; /* try the new value */
865 870
866 871 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
867 872 return (PSM_SUCCESS);
868 873 }
869 874
870 875 /* Now allocate the vectors */
871 876 if (hdlp->ih_type == DDI_INTR_TYPE_MSI) {
872 877 /* SET_PRI does not support the case of multiple MSI */
873 878 if (i_ddi_intr_get_current_nintrs(hdlp->ih_dip) > 1)
874 879 return (PSM_FAILURE);
875 880
876 881 count_vec = apic_alloc_msi_vectors(dip, hdlp->ih_inum,
877 882 1, new_priority,
878 883 DDI_INTR_ALLOC_STRICT);
879 884 } else {
880 885 count_vec = apic_alloc_msix_vectors(dip, hdlp->ih_inum,
881 886 1, new_priority,
882 887 DDI_INTR_ALLOC_STRICT);
883 888 }
884 889
885 890 /* Did we get new vectors? */
886 891 if (!count_vec)
887 892 return (PSM_FAILURE);
888 893
889 894 /* Finally, free the previously allocated vectors */
890 895 apic_free_vectors(dip, hdlp->ih_inum, count_vec,
891 896 old_priority, hdlp->ih_type);
892 897 break;
893 898 case PSM_INTR_OP_SET_CPU:
894 899 case PSM_INTR_OP_GRP_SET_CPU:
895 900 /*
896 901 * The interrupt handle given here has been allocated
897 902 * specifically for this command, and ih_private carries
898 903 * a CPU value.
899 904 */
900 905 new_cpu = (int)(intptr_t)hdlp->ih_private;
901 906 if (!apic_cpu_in_range(new_cpu)) {
902 907 DDI_INTR_IMPLDBG((CE_CONT,
903 908 "[grp_]set_cpu: cpu out of range: %d\n", new_cpu));
904 909 *result = EINVAL;
905 910 return (PSM_FAILURE);
906 911 }
907 912 if (hdlp->ih_vector > APIC_MAX_VECTOR) {
908 913 DDI_INTR_IMPLDBG((CE_CONT,
909 914 "[grp_]set_cpu: vector out of range: %d\n",
910 915 hdlp->ih_vector));
911 916 *result = EINVAL;
912 917 return (PSM_FAILURE);
913 918 }
914 919 if ((hdlp->ih_flags & PSMGI_INTRBY_FLAGS) == PSMGI_INTRBY_VEC)
915 920 hdlp->ih_vector = apic_vector_to_irq[hdlp->ih_vector];
916 921 if (intr_op == PSM_INTR_OP_SET_CPU) {
917 922 if (apic_set_cpu(hdlp->ih_vector, new_cpu, result) !=
918 923 PSM_SUCCESS)
919 924 return (PSM_FAILURE);
920 925 } else {
921 926 if (apic_grp_set_cpu(hdlp->ih_vector, new_cpu,
922 927 result) != PSM_SUCCESS)
923 928 return (PSM_FAILURE);
924 929 }
925 930 break;
926 931 case PSM_INTR_OP_GET_INTR:
927 932 /*
928 933 * The interrupt handle given here has been allocated
929 934 * specifically for this command, and ih_private carries
930 935 * a pointer to a apic_get_intr_t.
931 936 */
932 937 if (apic_get_vector_intr_info(
933 938 hdlp->ih_vector, hdlp->ih_private) != PSM_SUCCESS)
934 939 return (PSM_FAILURE);
935 940 break;
936 941 case PSM_INTR_OP_APIC_TYPE:
937 942 ((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
938 943 apic_get_apic_type();
939 944 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
940 945 APIC_MAX_VECTOR;
941 946 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
942 947 boot_ncpus;
943 948 hdlp->ih_ver = apic_get_apic_version();
944 949 break;
945 950 case PSM_INTR_OP_SET_CAP:
946 951 default:
947 952 return (PSM_FAILURE);
948 953 }
949 954 return (PSM_SUCCESS);
950 955 }
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