Print this page
don't block in nvme_bd_cmd
8628 nvme: use a semaphore to guard submission queue
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Jason King <jason.king@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/common/io/nvme/nvme.c
+++ new/usr/src/uts/common/io/nvme/nvme.c
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 16 * Copyright 2017 Joyent, Inc.
17 17 */
18 18
19 19 /*
20 20 * blkdev driver for NVMe compliant storage devices
21 21 *
22 22 * This driver was written to conform to version 1.2.1 of the NVMe
23 23 * specification. It may work with newer versions, but that is completely
24 24 * untested and disabled by default.
25 25 *
26 26 * The driver has only been tested on x86 systems and will not work on big-
27 27 * endian systems without changes to the code accessing registers and data
28 28 * structures used by the hardware.
29 29 *
30 30 *
31 31 * Interrupt Usage:
32 32 *
33 33 * The driver will use a single interrupt while configuring the device as the
34 34 * specification requires, but contrary to the specification it will try to use
35 35 * a single-message MSI(-X) or FIXED interrupt. Later in the attach process it
36 36 * will switch to multiple-message MSI(-X) if supported. The driver wants to
↓ open down ↓ |
36 lines elided |
↑ open up ↑ |
37 37 * have one interrupt vector per CPU, but it will work correctly if less are
38 38 * available. Interrupts can be shared by queues, the interrupt handler will
39 39 * iterate through the I/O queue array by steps of n_intr_cnt. Usually only
40 40 * the admin queue will share an interrupt with one I/O queue. The interrupt
41 41 * handler will retrieve completed commands from all queues sharing an interrupt
42 42 * vector and will post them to a taskq for completion processing.
43 43 *
44 44 *
45 45 * Command Processing:
46 46 *
47 - * NVMe devices can have up to 65536 I/O queue pairs, with each queue holding up
47 + * NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up
48 48 * to 65536 I/O commands. The driver will configure one I/O queue pair per
49 49 * available interrupt vector, with the queue length usually much smaller than
50 50 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
51 51 * interrupt vectors will be used.
52 52 *
53 53 * Additionally the hardware provides a single special admin queue pair that can
54 54 * hold up to 4096 admin commands.
55 55 *
56 56 * From the hardware perspective both queues of a queue pair are independent,
57 57 * but they share some driver state: the command array (holding pointers to
58 58 * commands currently being processed by the hardware) and the active command
59 59 * counter. Access to the submission side of a queue pair and the shared state
60 60 * is protected by nq_mutex. The completion side of a queue pair does not need
61 61 * that protection apart from its access to the shared state; it is called only
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
62 62 * in the interrupt handler which does not run concurrently for the same
63 63 * interrupt vector.
64 64 *
65 65 * When a command is submitted to a queue pair the active command counter is
66 66 * incremented and a pointer to the command is stored in the command array. The
67 67 * array index is used as command identifier (CID) in the submission queue
68 68 * entry. Some commands may take a very long time to complete, and if the queue
69 69 * wraps around in that time a submission may find the next array slot to still
70 70 * be used by a long-running command. In this case the array is sequentially
71 71 * searched for the next free slot. The length of the command array is the same
72 - * as the configured queue length.
72 + * as the configured queue length. Queue overrun is prevented by the semaphore,
73 + * so a command submission may block if the queue is full.
73 74 *
74 75 *
75 76 * Polled I/O Support:
76 77 *
77 78 * For kernel core dump support the driver can do polled I/O. As interrupts are
78 79 * turned off while dumping the driver will just submit a command in the regular
79 80 * way, and then repeatedly attempt a command retrieval until it gets the
80 81 * command back.
81 82 *
82 83 *
83 84 * Namespace Support:
84 85 *
85 86 * NVMe devices can have multiple namespaces, each being a independent data
86 87 * store. The driver supports multiple namespaces and creates a blkdev interface
87 88 * for each namespace found. Namespaces can have various attributes to support
88 89 * thin provisioning and protection information. This driver does not support
89 90 * any of this and ignores namespaces that have these attributes.
90 91 *
91 92 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier
92 93 * (EUI64). This driver uses the EUI64 if present to generate the devid and
93 94 * passes it to blkdev to use it in the device node names. As this is currently
94 95 * untested namespaces with EUI64 are ignored by default.
95 96 *
96 97 * We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a
97 98 * single controller. This is an artificial limit imposed by the driver to be
98 99 * able to address a reasonable number of controllers and namespaces using a
99 100 * 32bit minor node number.
100 101 *
101 102 *
102 103 * Minor nodes:
103 104 *
104 105 * For each NVMe device the driver exposes one minor node for the controller and
105 106 * one minor node for each namespace. The only operations supported by those
106 107 * minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the
107 108 * interface for the nvmeadm(1M) utility.
108 109 *
109 110 *
110 111 * Blkdev Interface:
111 112 *
112 113 * This driver uses blkdev to do all the heavy lifting involved with presenting
113 114 * a disk device to the system. As a result, the processing of I/O requests is
114 115 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
115 116 * setup, and splitting of transfers into manageable chunks.
116 117 *
117 118 * I/O requests coming in from blkdev are turned into NVM commands and posted to
118 119 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
119 120 * queues. There is currently no timeout handling of I/O commands.
120 121 *
121 122 * Blkdev also supports querying device/media information and generating a
122 123 * devid. The driver reports the best block size as determined by the namespace
123 124 * format back to blkdev as physical block size to support partition and block
124 125 * alignment. The devid is either based on the namespace EUI64, if present, or
125 126 * composed using the device vendor ID, model number, serial number, and the
126 127 * namespace ID.
127 128 *
128 129 *
129 130 * Error Handling:
130 131 *
131 132 * Error handling is currently limited to detecting fatal hardware errors,
132 133 * either by asynchronous events, or synchronously through command status or
133 134 * admin command timeouts. In case of severe errors the device is fenced off,
134 135 * all further requests will return EIO. FMA is then called to fault the device.
135 136 *
136 137 * The hardware has a limit for outstanding asynchronous event requests. Before
137 138 * this limit is known the driver assumes it is at least 1 and posts a single
138 139 * asynchronous request. Later when the limit is known more asynchronous event
139 140 * requests are posted to allow quicker reception of error information. When an
140 141 * asynchronous event is posted by the hardware the driver will parse the error
141 142 * status fields and log information or fault the device, depending on the
142 143 * severity of the asynchronous event. The asynchronous event request is then
143 144 * reused and posted to the admin queue again.
144 145 *
145 146 * On command completion the command status is checked for errors. In case of
146 147 * errors indicating a driver bug the driver panics. Almost all other error
147 148 * status values just cause EIO to be returned.
148 149 *
149 150 * Command timeouts are currently detected for all admin commands except
150 151 * asynchronous event requests. If a command times out and the hardware appears
151 152 * to be healthy the driver attempts to abort the command. If this fails the
152 153 * driver assumes the device to be dead, fences it off, and calls FMA to retire
153 154 * it. In general admin commands are issued at attach time only. No timeout
154 155 * handling of normal I/O commands is presently done.
155 156 *
156 157 * In some cases it may be possible that the ABORT command times out, too. In
157 158 * that case the device is also declared dead and fenced off.
158 159 *
159 160 *
160 161 * Quiesce / Fast Reboot:
161 162 *
162 163 * The driver currently does not support fast reboot. A quiesce(9E) entry point
163 164 * is still provided which is used to send a shutdown notification to the
164 165 * device.
165 166 *
166 167 *
167 168 * Driver Configuration:
168 169 *
169 170 * The following driver properties can be changed to control some aspects of the
170 171 * drivers operation:
171 172 * - strict-version: can be set to 0 to allow devices conforming to newer
172 173 * versions or namespaces with EUI64 to be used
173 174 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
174 175 * specific command status as a fatal error leading device faulting
175 176 * - admin-queue-len: the maximum length of the admin queue (16-4096)
176 177 * - io-queue-len: the maximum length of the I/O queues (16-65536)
177 178 * - async-event-limit: the maximum number of asynchronous event requests to be
178 179 * posted by the driver
179 180 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write
180 181 * cache
181 182 * - min-phys-block-size: the minimum physical block size to report to blkdev,
182 183 * which is among other things the basis for ZFS vdev ashift
183 184 *
184 185 *
185 186 * TODO:
186 187 * - figure out sane default for I/O queue depth reported to blkdev
187 188 * - FMA handling of media errors
188 189 * - support for devices supporting very large I/O requests using chained PRPs
189 190 * - support for configuring hardware parameters like interrupt coalescing
190 191 * - support for media formatting and hard partitioning into namespaces
191 192 * - support for big-endian systems
192 193 * - support for fast reboot
193 194 * - support for firmware updates
194 195 * - support for NVMe Subsystem Reset (1.1)
195 196 * - support for Scatter/Gather lists (1.1)
196 197 * - support for Reservations (1.1)
197 198 * - support for power management
198 199 */
199 200
200 201 #include <sys/byteorder.h>
201 202 #ifdef _BIG_ENDIAN
202 203 #error nvme driver needs porting for big-endian platforms
203 204 #endif
204 205
205 206 #include <sys/modctl.h>
206 207 #include <sys/conf.h>
207 208 #include <sys/devops.h>
208 209 #include <sys/ddi.h>
209 210 #include <sys/sunddi.h>
210 211 #include <sys/sunndi.h>
211 212 #include <sys/bitmap.h>
212 213 #include <sys/sysmacros.h>
213 214 #include <sys/param.h>
214 215 #include <sys/varargs.h>
215 216 #include <sys/cpuvar.h>
216 217 #include <sys/disp.h>
217 218 #include <sys/blkdev.h>
218 219 #include <sys/atomic.h>
219 220 #include <sys/archsystm.h>
220 221 #include <sys/sata/sata_hba.h>
221 222 #include <sys/stat.h>
222 223 #include <sys/policy.h>
223 224
224 225 #include <sys/nvme.h>
225 226
226 227 #ifdef __x86
227 228 #include <sys/x86_archext.h>
228 229 #endif
229 230
230 231 #include "nvme_reg.h"
231 232 #include "nvme_var.h"
232 233
233 234
234 235 /* NVMe spec version supported */
235 236 static const int nvme_version_major = 1;
236 237 static const int nvme_version_minor = 2;
237 238
238 239 /* tunable for admin command timeout in seconds, default is 1s */
239 240 int nvme_admin_cmd_timeout = 1;
240 241
241 242 /* tunable for FORMAT NVM command timeout in seconds, default is 600s */
242 243 int nvme_format_cmd_timeout = 600;
243 244
244 245 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
245 246 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
246 247 static int nvme_quiesce(dev_info_t *);
247 248 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
248 249 static int nvme_setup_interrupts(nvme_t *, int, int);
249 250 static void nvme_release_interrupts(nvme_t *);
↓ open down ↓ |
167 lines elided |
↑ open up ↑ |
250 251 static uint_t nvme_intr(caddr_t, caddr_t);
251 252
252 253 static void nvme_shutdown(nvme_t *, int, boolean_t);
253 254 static boolean_t nvme_reset(nvme_t *, boolean_t);
254 255 static int nvme_init(nvme_t *);
255 256 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
256 257 static void nvme_free_cmd(nvme_cmd_t *);
257 258 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
258 259 bd_xfer_t *);
259 260 static int nvme_admin_cmd(nvme_cmd_t *, int);
260 -static int nvme_submit_cmd(nvme_qpair_t *, nvme_cmd_t *);
261 +static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *);
262 +static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *);
263 +static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *);
261 264 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
262 265 static boolean_t nvme_wait_cmd(nvme_cmd_t *, uint_t);
263 266 static void nvme_wakeup_cmd(void *);
264 267 static void nvme_async_event_task(void *);
265 268
266 269 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
267 270 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
268 271 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
269 272 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
270 273 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
271 274 static inline int nvme_check_cmd_status(nvme_cmd_t *);
272 275
273 276 static void nvme_abort_cmd(nvme_cmd_t *);
274 -static int nvme_async_event(nvme_t *);
277 +static void nvme_async_event(nvme_t *);
275 278 static int nvme_format_nvm(nvme_t *, uint32_t, uint8_t, boolean_t, uint8_t,
276 279 boolean_t, uint8_t);
277 280 static int nvme_get_logpage(nvme_t *, void **, size_t *, uint8_t, ...);
278 281 static void *nvme_identify(nvme_t *, uint32_t);
279 282 static boolean_t nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t,
280 283 uint32_t *);
281 284 static boolean_t nvme_get_features(nvme_t *, uint32_t, uint8_t, uint32_t *,
282 285 void **, size_t *);
283 286 static boolean_t nvme_write_cache_set(nvme_t *, boolean_t);
284 287 static int nvme_set_nqueues(nvme_t *, uint16_t);
285 288
286 289 static void nvme_free_dma(nvme_dma_t *);
287 290 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
288 291 nvme_dma_t **);
289 292 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
290 293 nvme_dma_t **);
291 294 static void nvme_free_qpair(nvme_qpair_t *);
292 295 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
293 296 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
294 297
295 298 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
296 299 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
297 300 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
298 301 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
299 302
300 303 static boolean_t nvme_check_regs_hdl(nvme_t *);
301 304 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
302 305
303 306 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
304 307
305 308 static void nvme_bd_xfer_done(void *);
306 309 static void nvme_bd_driveinfo(void *, bd_drive_t *);
307 310 static int nvme_bd_mediainfo(void *, bd_media_t *);
308 311 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
309 312 static int nvme_bd_read(void *, bd_xfer_t *);
310 313 static int nvme_bd_write(void *, bd_xfer_t *);
311 314 static int nvme_bd_sync(void *, bd_xfer_t *);
312 315 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
313 316
314 317 static int nvme_prp_dma_constructor(void *, void *, int);
315 318 static void nvme_prp_dma_destructor(void *, void *);
316 319
317 320 static void nvme_prepare_devid(nvme_t *, uint32_t);
318 321
319 322 static int nvme_open(dev_t *, int, int, cred_t *);
320 323 static int nvme_close(dev_t, int, int, cred_t *);
321 324 static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
322 325
323 326 #define NVME_MINOR_INST_SHIFT 9
324 327 #define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid))
325 328 #define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT)
326 329 #define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1))
327 330 #define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2)
328 331
329 332 static void *nvme_state;
330 333 static kmem_cache_t *nvme_cmd_cache;
331 334
332 335 /*
333 336 * DMA attributes for queue DMA memory
334 337 *
335 338 * Queue DMA memory must be page aligned. The maximum length of a queue is
336 339 * 65536 entries, and an entry can be 64 bytes long.
337 340 */
338 341 static ddi_dma_attr_t nvme_queue_dma_attr = {
339 342 .dma_attr_version = DMA_ATTR_V0,
340 343 .dma_attr_addr_lo = 0,
341 344 .dma_attr_addr_hi = 0xffffffffffffffffULL,
342 345 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
343 346 .dma_attr_align = 0x1000,
344 347 .dma_attr_burstsizes = 0x7ff,
345 348 .dma_attr_minxfer = 0x1000,
346 349 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
347 350 .dma_attr_seg = 0xffffffffffffffffULL,
348 351 .dma_attr_sgllen = 1,
349 352 .dma_attr_granular = 1,
350 353 .dma_attr_flags = 0,
351 354 };
352 355
353 356 /*
354 357 * DMA attributes for transfers using Physical Region Page (PRP) entries
355 358 *
356 359 * A PRP entry describes one page of DMA memory using the page size specified
357 360 * in the controller configuration's memory page size register (CC.MPS). It uses
358 361 * a 64bit base address aligned to this page size. There is no limitation on
359 362 * chaining PRPs together for arbitrarily large DMA transfers.
360 363 */
361 364 static ddi_dma_attr_t nvme_prp_dma_attr = {
362 365 .dma_attr_version = DMA_ATTR_V0,
363 366 .dma_attr_addr_lo = 0,
364 367 .dma_attr_addr_hi = 0xffffffffffffffffULL,
365 368 .dma_attr_count_max = 0xfff,
366 369 .dma_attr_align = 0x1000,
367 370 .dma_attr_burstsizes = 0x7ff,
368 371 .dma_attr_minxfer = 0x1000,
369 372 .dma_attr_maxxfer = 0x1000,
370 373 .dma_attr_seg = 0xfff,
371 374 .dma_attr_sgllen = -1,
372 375 .dma_attr_granular = 1,
373 376 .dma_attr_flags = 0,
374 377 };
375 378
376 379 /*
377 380 * DMA attributes for transfers using scatter/gather lists
378 381 *
379 382 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
380 383 * 32bit length field. SGL Segment and SGL Last Segment entries require the
381 384 * length to be a multiple of 16 bytes.
382 385 */
383 386 static ddi_dma_attr_t nvme_sgl_dma_attr = {
384 387 .dma_attr_version = DMA_ATTR_V0,
385 388 .dma_attr_addr_lo = 0,
386 389 .dma_attr_addr_hi = 0xffffffffffffffffULL,
387 390 .dma_attr_count_max = 0xffffffffUL,
388 391 .dma_attr_align = 1,
389 392 .dma_attr_burstsizes = 0x7ff,
390 393 .dma_attr_minxfer = 0x10,
391 394 .dma_attr_maxxfer = 0xfffffffffULL,
392 395 .dma_attr_seg = 0xffffffffffffffffULL,
393 396 .dma_attr_sgllen = -1,
394 397 .dma_attr_granular = 0x10,
395 398 .dma_attr_flags = 0
396 399 };
397 400
398 401 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
399 402 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
400 403 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
401 404 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
402 405 };
403 406
404 407 static struct cb_ops nvme_cb_ops = {
405 408 .cb_open = nvme_open,
406 409 .cb_close = nvme_close,
407 410 .cb_strategy = nodev,
408 411 .cb_print = nodev,
409 412 .cb_dump = nodev,
410 413 .cb_read = nodev,
411 414 .cb_write = nodev,
412 415 .cb_ioctl = nvme_ioctl,
413 416 .cb_devmap = nodev,
414 417 .cb_mmap = nodev,
415 418 .cb_segmap = nodev,
416 419 .cb_chpoll = nochpoll,
417 420 .cb_prop_op = ddi_prop_op,
418 421 .cb_str = 0,
419 422 .cb_flag = D_NEW | D_MP,
420 423 .cb_rev = CB_REV,
421 424 .cb_aread = nodev,
422 425 .cb_awrite = nodev
423 426 };
424 427
425 428 static struct dev_ops nvme_dev_ops = {
426 429 .devo_rev = DEVO_REV,
427 430 .devo_refcnt = 0,
428 431 .devo_getinfo = ddi_no_info,
429 432 .devo_identify = nulldev,
430 433 .devo_probe = nulldev,
431 434 .devo_attach = nvme_attach,
432 435 .devo_detach = nvme_detach,
433 436 .devo_reset = nodev,
434 437 .devo_cb_ops = &nvme_cb_ops,
435 438 .devo_bus_ops = NULL,
436 439 .devo_power = NULL,
437 440 .devo_quiesce = nvme_quiesce,
438 441 };
439 442
440 443 static struct modldrv nvme_modldrv = {
441 444 .drv_modops = &mod_driverops,
442 445 .drv_linkinfo = "NVMe v1.1b",
443 446 .drv_dev_ops = &nvme_dev_ops
444 447 };
445 448
446 449 static struct modlinkage nvme_modlinkage = {
447 450 .ml_rev = MODREV_1,
448 451 .ml_linkage = { &nvme_modldrv, NULL }
449 452 };
450 453
451 454 static bd_ops_t nvme_bd_ops = {
452 455 .o_version = BD_OPS_VERSION_0,
453 456 .o_drive_info = nvme_bd_driveinfo,
454 457 .o_media_info = nvme_bd_mediainfo,
455 458 .o_devid_init = nvme_bd_devid,
456 459 .o_sync_cache = nvme_bd_sync,
457 460 .o_read = nvme_bd_read,
458 461 .o_write = nvme_bd_write,
459 462 };
460 463
461 464 int
462 465 _init(void)
463 466 {
464 467 int error;
465 468
466 469 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
467 470 if (error != DDI_SUCCESS)
468 471 return (error);
469 472
470 473 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
471 474 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
472 475
473 476 bd_mod_init(&nvme_dev_ops);
474 477
475 478 error = mod_install(&nvme_modlinkage);
476 479 if (error != DDI_SUCCESS) {
477 480 ddi_soft_state_fini(&nvme_state);
478 481 bd_mod_fini(&nvme_dev_ops);
479 482 }
480 483
481 484 return (error);
482 485 }
483 486
484 487 int
485 488 _fini(void)
486 489 {
487 490 int error;
488 491
489 492 error = mod_remove(&nvme_modlinkage);
490 493 if (error == DDI_SUCCESS) {
491 494 ddi_soft_state_fini(&nvme_state);
492 495 kmem_cache_destroy(nvme_cmd_cache);
493 496 bd_mod_fini(&nvme_dev_ops);
494 497 }
495 498
496 499 return (error);
497 500 }
498 501
499 502 int
500 503 _info(struct modinfo *modinfop)
501 504 {
502 505 return (mod_info(&nvme_modlinkage, modinfop));
503 506 }
504 507
505 508 static inline void
506 509 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
507 510 {
508 511 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
509 512
510 513 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
511 514 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
512 515 }
513 516
514 517 static inline void
515 518 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
516 519 {
517 520 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
518 521
519 522 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
520 523 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
521 524 }
522 525
523 526 static inline uint64_t
524 527 nvme_get64(nvme_t *nvme, uintptr_t reg)
525 528 {
526 529 uint64_t val;
527 530
528 531 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
529 532
530 533 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
531 534 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
532 535
533 536 return (val);
534 537 }
535 538
536 539 static inline uint32_t
537 540 nvme_get32(nvme_t *nvme, uintptr_t reg)
538 541 {
539 542 uint32_t val;
540 543
541 544 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
542 545
543 546 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
544 547 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
545 548
546 549 return (val);
547 550 }
548 551
549 552 static boolean_t
550 553 nvme_check_regs_hdl(nvme_t *nvme)
551 554 {
552 555 ddi_fm_error_t error;
553 556
554 557 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
555 558
556 559 if (error.fme_status != DDI_FM_OK)
557 560 return (B_TRUE);
558 561
559 562 return (B_FALSE);
560 563 }
561 564
562 565 static boolean_t
563 566 nvme_check_dma_hdl(nvme_dma_t *dma)
564 567 {
565 568 ddi_fm_error_t error;
566 569
567 570 if (dma == NULL)
568 571 return (B_FALSE);
569 572
570 573 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
571 574
572 575 if (error.fme_status != DDI_FM_OK)
573 576 return (B_TRUE);
574 577
575 578 return (B_FALSE);
576 579 }
577 580
578 581 static void
579 582 nvme_free_dma_common(nvme_dma_t *dma)
580 583 {
581 584 if (dma->nd_dmah != NULL)
582 585 (void) ddi_dma_unbind_handle(dma->nd_dmah);
583 586 if (dma->nd_acch != NULL)
584 587 ddi_dma_mem_free(&dma->nd_acch);
585 588 if (dma->nd_dmah != NULL)
586 589 ddi_dma_free_handle(&dma->nd_dmah);
587 590 }
588 591
589 592 static void
590 593 nvme_free_dma(nvme_dma_t *dma)
591 594 {
592 595 nvme_free_dma_common(dma);
593 596 kmem_free(dma, sizeof (*dma));
594 597 }
595 598
596 599 /* ARGSUSED */
597 600 static void
598 601 nvme_prp_dma_destructor(void *buf, void *private)
599 602 {
600 603 nvme_dma_t *dma = (nvme_dma_t *)buf;
601 604
602 605 nvme_free_dma_common(dma);
603 606 }
604 607
605 608 static int
606 609 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
607 610 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
608 611 {
609 612 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
610 613 &dma->nd_dmah) != DDI_SUCCESS) {
611 614 /*
612 615 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
613 616 * the only other possible error is DDI_DMA_BADATTR which
614 617 * indicates a driver bug which should cause a panic.
615 618 */
616 619 dev_err(nvme->n_dip, CE_PANIC,
617 620 "!failed to get DMA handle, check DMA attributes");
618 621 return (DDI_FAILURE);
619 622 }
620 623
621 624 /*
622 625 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
623 626 * or the flags are conflicting, which isn't the case here.
624 627 */
625 628 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
626 629 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
627 630 &dma->nd_len, &dma->nd_acch);
628 631
629 632 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
630 633 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
631 634 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
632 635 dev_err(nvme->n_dip, CE_WARN,
633 636 "!failed to bind DMA memory");
634 637 atomic_inc_32(&nvme->n_dma_bind_err);
635 638 nvme_free_dma_common(dma);
636 639 return (DDI_FAILURE);
637 640 }
638 641
639 642 return (DDI_SUCCESS);
640 643 }
641 644
642 645 static int
643 646 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
644 647 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
645 648 {
646 649 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
647 650
648 651 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
649 652 DDI_SUCCESS) {
650 653 *ret = NULL;
651 654 kmem_free(dma, sizeof (nvme_dma_t));
652 655 return (DDI_FAILURE);
653 656 }
654 657
655 658 bzero(dma->nd_memp, dma->nd_len);
656 659
657 660 *ret = dma;
658 661 return (DDI_SUCCESS);
659 662 }
660 663
661 664 /* ARGSUSED */
662 665 static int
663 666 nvme_prp_dma_constructor(void *buf, void *private, int flags)
664 667 {
665 668 nvme_dma_t *dma = (nvme_dma_t *)buf;
666 669 nvme_t *nvme = (nvme_t *)private;
667 670
668 671 dma->nd_dmah = NULL;
669 672 dma->nd_acch = NULL;
670 673
671 674 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
672 675 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
673 676 return (-1);
674 677 }
675 678
676 679 ASSERT(dma->nd_ncookie == 1);
677 680
678 681 dma->nd_cached = B_TRUE;
679 682
680 683 return (0);
681 684 }
682 685
683 686 static int
684 687 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
685 688 uint_t flags, nvme_dma_t **dma)
686 689 {
687 690 uint32_t len = nentry * qe_len;
688 691 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
689 692
690 693 len = roundup(len, nvme->n_pagesize);
691 694
692 695 q_dma_attr.dma_attr_minxfer = len;
693 696
694 697 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
695 698 != DDI_SUCCESS) {
696 699 dev_err(nvme->n_dip, CE_WARN,
697 700 "!failed to get DMA memory for queue");
698 701 goto fail;
699 702 }
700 703
701 704 if ((*dma)->nd_ncookie != 1) {
702 705 dev_err(nvme->n_dip, CE_WARN,
703 706 "!got too many cookies for queue DMA");
704 707 goto fail;
705 708 }
706 709
707 710 return (DDI_SUCCESS);
708 711
709 712 fail:
710 713 if (*dma) {
711 714 nvme_free_dma(*dma);
712 715 *dma = NULL;
713 716 }
↓ open down ↓ |
429 lines elided |
↑ open up ↑ |
714 717
715 718 return (DDI_FAILURE);
716 719 }
717 720
718 721 static void
719 722 nvme_free_qpair(nvme_qpair_t *qp)
720 723 {
721 724 int i;
722 725
723 726 mutex_destroy(&qp->nq_mutex);
727 + sema_destroy(&qp->nq_sema);
724 728
725 729 if (qp->nq_sqdma != NULL)
726 730 nvme_free_dma(qp->nq_sqdma);
727 731 if (qp->nq_cqdma != NULL)
728 732 nvme_free_dma(qp->nq_cqdma);
729 733
730 734 if (qp->nq_active_cmds > 0)
731 735 for (i = 0; i != qp->nq_nentry; i++)
732 736 if (qp->nq_cmd[i] != NULL)
733 737 nvme_free_cmd(qp->nq_cmd[i]);
734 738
735 739 if (qp->nq_cmd != NULL)
736 740 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
737 741
738 742 kmem_free(qp, sizeof (nvme_qpair_t));
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
739 743 }
740 744
741 745 static int
742 746 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
743 747 int idx)
744 748 {
745 749 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
746 750
747 751 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
748 752 DDI_INTR_PRI(nvme->n_intr_pri));
753 + sema_init(&qp->nq_sema, nentry, NULL, SEMA_DRIVER, NULL);
749 754
750 755 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
751 756 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
752 757 goto fail;
753 758
754 759 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
755 760 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
756 761 goto fail;
757 762
758 763 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
759 764 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
760 765 qp->nq_nentry = nentry;
761 766
762 767 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
763 768 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
764 769
765 770 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
766 771 qp->nq_next_cmd = 0;
767 772
768 773 *nqp = qp;
769 774 return (DDI_SUCCESS);
770 775
771 776 fail:
772 777 nvme_free_qpair(qp);
773 778 *nqp = NULL;
774 779
775 780 return (DDI_FAILURE);
776 781 }
777 782
778 783 static nvme_cmd_t *
779 784 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
780 785 {
781 786 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
782 787
783 788 if (cmd == NULL)
784 789 return (cmd);
785 790
786 791 bzero(cmd, sizeof (nvme_cmd_t));
787 792
788 793 cmd->nc_nvme = nvme;
789 794
790 795 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
791 796 DDI_INTR_PRI(nvme->n_intr_pri));
792 797 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
793 798
794 799 return (cmd);
795 800 }
796 801
797 802 static void
798 803 nvme_free_cmd(nvme_cmd_t *cmd)
799 804 {
800 805 if (cmd->nc_dma) {
801 806 if (cmd->nc_dma->nd_cached)
802 807 kmem_cache_free(cmd->nc_nvme->n_prp_cache,
803 808 cmd->nc_dma);
804 809 else
↓ open down ↓ |
46 lines elided |
↑ open up ↑ |
805 810 nvme_free_dma(cmd->nc_dma);
806 811 cmd->nc_dma = NULL;
807 812 }
808 813
809 814 cv_destroy(&cmd->nc_cv);
810 815 mutex_destroy(&cmd->nc_mutex);
811 816
812 817 kmem_cache_free(nvme_cmd_cache, cmd);
813 818 }
814 819
820 +static void
821 +nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
822 +{
823 + sema_p(&qp->nq_sema);
824 + nvme_submit_cmd_common(qp, cmd);
825 +}
826 +
815 827 static int
816 -nvme_submit_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
828 +nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
817 829 {
818 - nvme_reg_sqtdbl_t tail = { 0 };
830 + if (sema_tryp(&qp->nq_sema) == 0)
831 + return (EAGAIN);
819 832
820 - mutex_enter(&qp->nq_mutex);
833 + nvme_submit_cmd_common(qp, cmd);
834 + return (0);
835 +}
821 836
822 - if (qp->nq_active_cmds == qp->nq_nentry) {
823 - mutex_exit(&qp->nq_mutex);
824 - return (DDI_FAILURE);
825 - }
837 +static void
838 +nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd)
839 +{
840 + nvme_reg_sqtdbl_t tail = { 0 };
826 841
842 + mutex_enter(&qp->nq_mutex);
827 843 cmd->nc_completed = B_FALSE;
828 844
829 845 /*
830 846 * Try to insert the cmd into the active cmd array at the nq_next_cmd
831 847 * slot. If the slot is already occupied advance to the next slot and
832 848 * try again. This can happen for long running commands like async event
833 849 * requests.
834 850 */
835 851 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
836 852 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
837 853 qp->nq_cmd[qp->nq_next_cmd] = cmd;
838 854
839 855 qp->nq_active_cmds++;
840 856
841 857 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
842 858 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
843 859 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
844 860 sizeof (nvme_sqe_t) * qp->nq_sqtail,
845 861 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
846 862 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
847 863
848 864 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
849 865 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
850 866
851 867 mutex_exit(&qp->nq_mutex);
852 - return (DDI_SUCCESS);
853 868 }
854 869
855 870 static nvme_cmd_t *
856 871 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
857 872 {
858 873 nvme_reg_cqhdbl_t head = { 0 };
859 874
860 875 nvme_cqe_t *cqe;
861 876 nvme_cmd_t *cmd;
862 877
863 878 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
864 879 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
865 880
866 881 mutex_enter(&qp->nq_mutex);
867 882 cqe = &qp->nq_cq[qp->nq_cqhead];
868 883
869 884 /* Check phase tag of CQE. Hardware inverts it for new entries. */
870 885 if (cqe->cqe_sf.sf_p == qp->nq_phase) {
871 886 mutex_exit(&qp->nq_mutex);
872 887 return (NULL);
873 888 }
874 889
875 890 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
876 891 ASSERT(cqe->cqe_cid < qp->nq_nentry);
877 892
878 893 cmd = qp->nq_cmd[cqe->cqe_cid];
879 894 qp->nq_cmd[cqe->cqe_cid] = NULL;
880 895 qp->nq_active_cmds--;
881 896
882 897 ASSERT(cmd != NULL);
883 898 ASSERT(cmd->nc_nvme == nvme);
884 899 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
885 900 ASSERT(cmd->nc_sqe.sqe_cid == cqe->cqe_cid);
886 901 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
887 902
↓ open down ↓ |
25 lines elided |
↑ open up ↑ |
888 903 qp->nq_sqhead = cqe->cqe_sqhd;
889 904
890 905 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
891 906
892 907 /* Toggle phase on wrap-around. */
893 908 if (qp->nq_cqhead == 0)
894 909 qp->nq_phase = qp->nq_phase ? 0 : 1;
895 910
896 911 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r);
897 912 mutex_exit(&qp->nq_mutex);
913 + sema_v(&qp->nq_sema);
898 914
899 915 return (cmd);
900 916 }
901 917
902 918 static int
903 919 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
904 920 {
905 921 nvme_cqe_t *cqe = &cmd->nc_cqe;
906 922
907 923 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
908 924 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
909 925 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
910 926 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
911 927 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
912 928
913 929 if (cmd->nc_xfer != NULL)
914 930 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
915 931
916 932 if (cmd->nc_nvme->n_strict_version) {
917 933 cmd->nc_nvme->n_dead = B_TRUE;
918 934 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
919 935 }
920 936
921 937 return (EIO);
922 938 }
923 939
924 940 static int
925 941 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
926 942 {
927 943 nvme_cqe_t *cqe = &cmd->nc_cqe;
928 944
929 945 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
930 946 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
931 947 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
932 948 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
933 949 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
934 950 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
935 951 cmd->nc_nvme->n_dead = B_TRUE;
936 952 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
937 953 }
938 954
939 955 return (EIO);
940 956 }
941 957
942 958 static int
943 959 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
944 960 {
945 961 nvme_cqe_t *cqe = &cmd->nc_cqe;
946 962
947 963 switch (cqe->cqe_sf.sf_sc) {
948 964 case NVME_CQE_SC_INT_NVM_WRITE:
949 965 /* write fail */
950 966 /* TODO: post ereport */
951 967 if (cmd->nc_xfer != NULL)
952 968 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
953 969 return (EIO);
954 970
955 971 case NVME_CQE_SC_INT_NVM_READ:
956 972 /* read fail */
957 973 /* TODO: post ereport */
958 974 if (cmd->nc_xfer != NULL)
959 975 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
960 976 return (EIO);
961 977
962 978 default:
963 979 return (nvme_check_unknown_cmd_status(cmd));
964 980 }
965 981 }
966 982
967 983 static int
968 984 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
969 985 {
970 986 nvme_cqe_t *cqe = &cmd->nc_cqe;
971 987
972 988 switch (cqe->cqe_sf.sf_sc) {
973 989 case NVME_CQE_SC_GEN_SUCCESS:
974 990 return (0);
975 991
976 992 /*
977 993 * Errors indicating a bug in the driver should cause a panic.
978 994 */
979 995 case NVME_CQE_SC_GEN_INV_OPC:
980 996 /* Invalid Command Opcode */
981 997 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
982 998 "invalid opcode in cmd %p", (void *)cmd);
983 999 return (0);
984 1000
985 1001 case NVME_CQE_SC_GEN_INV_FLD:
986 1002 /* Invalid Field in Command */
987 1003 if (!cmd->nc_dontpanic)
988 1004 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
989 1005 "programming error: invalid field in cmd %p",
990 1006 (void *)cmd);
991 1007 return (EIO);
992 1008
993 1009 case NVME_CQE_SC_GEN_ID_CNFL:
994 1010 /* Command ID Conflict */
995 1011 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
996 1012 "cmd ID conflict in cmd %p", (void *)cmd);
997 1013 return (0);
998 1014
999 1015 case NVME_CQE_SC_GEN_INV_NS:
1000 1016 /* Invalid Namespace or Format */
1001 1017 if (!cmd->nc_dontpanic)
1002 1018 dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
1003 1019 "programming error: " "invalid NS/format in cmd %p",
1004 1020 (void *)cmd);
1005 1021 return (EINVAL);
1006 1022
1007 1023 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
1008 1024 /* LBA Out Of Range */
1009 1025 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1010 1026 "LBA out of range in cmd %p", (void *)cmd);
1011 1027 return (0);
1012 1028
1013 1029 /*
1014 1030 * Non-fatal errors, handle gracefully.
1015 1031 */
1016 1032 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
1017 1033 /* Data Transfer Error (DMA) */
1018 1034 /* TODO: post ereport */
1019 1035 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
1020 1036 if (cmd->nc_xfer != NULL)
1021 1037 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1022 1038 return (EIO);
1023 1039
1024 1040 case NVME_CQE_SC_GEN_INTERNAL_ERR:
1025 1041 /*
1026 1042 * Internal Error. The spec (v1.0, section 4.5.1.2) says
1027 1043 * detailed error information is returned as async event,
1028 1044 * so we pretty much ignore the error here and handle it
1029 1045 * in the async event handler.
1030 1046 */
1031 1047 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
1032 1048 if (cmd->nc_xfer != NULL)
1033 1049 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1034 1050 return (EIO);
1035 1051
1036 1052 case NVME_CQE_SC_GEN_ABORT_REQUEST:
1037 1053 /*
1038 1054 * Command Abort Requested. This normally happens only when a
1039 1055 * command times out.
1040 1056 */
1041 1057 /* TODO: post ereport or change blkdev to handle this? */
1042 1058 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
1043 1059 return (ECANCELED);
1044 1060
1045 1061 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
1046 1062 /* Command Aborted due to Power Loss Notification */
1047 1063 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
1048 1064 cmd->nc_nvme->n_dead = B_TRUE;
1049 1065 return (EIO);
1050 1066
1051 1067 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
1052 1068 /* Command Aborted due to SQ Deletion */
1053 1069 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
1054 1070 return (EIO);
1055 1071
1056 1072 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
1057 1073 /* Capacity Exceeded */
1058 1074 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
1059 1075 if (cmd->nc_xfer != NULL)
1060 1076 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
1061 1077 return (EIO);
1062 1078
1063 1079 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
1064 1080 /* Namespace Not Ready */
1065 1081 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
1066 1082 if (cmd->nc_xfer != NULL)
1067 1083 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
1068 1084 return (EIO);
1069 1085
1070 1086 default:
1071 1087 return (nvme_check_unknown_cmd_status(cmd));
1072 1088 }
1073 1089 }
1074 1090
1075 1091 static int
1076 1092 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
1077 1093 {
1078 1094 nvme_cqe_t *cqe = &cmd->nc_cqe;
1079 1095
1080 1096 switch (cqe->cqe_sf.sf_sc) {
1081 1097 case NVME_CQE_SC_SPC_INV_CQ:
1082 1098 /* Completion Queue Invalid */
1083 1099 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
1084 1100 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
1085 1101 return (EINVAL);
1086 1102
1087 1103 case NVME_CQE_SC_SPC_INV_QID:
1088 1104 /* Invalid Queue Identifier */
1089 1105 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1090 1106 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
1091 1107 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
1092 1108 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1093 1109 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
1094 1110 return (EINVAL);
1095 1111
1096 1112 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
1097 1113 /* Max Queue Size Exceeded */
1098 1114 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1099 1115 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1100 1116 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
1101 1117 return (EINVAL);
1102 1118
1103 1119 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
1104 1120 /* Abort Command Limit Exceeded */
1105 1121 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
1106 1122 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1107 1123 "abort command limit exceeded in cmd %p", (void *)cmd);
1108 1124 return (0);
1109 1125
1110 1126 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
1111 1127 /* Async Event Request Limit Exceeded */
1112 1128 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
1113 1129 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1114 1130 "async event request limit exceeded in cmd %p",
1115 1131 (void *)cmd);
1116 1132 return (0);
1117 1133
1118 1134 case NVME_CQE_SC_SPC_INV_INT_VECT:
1119 1135 /* Invalid Interrupt Vector */
1120 1136 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1121 1137 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
1122 1138 return (EINVAL);
1123 1139
1124 1140 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
1125 1141 /* Invalid Log Page */
1126 1142 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
1127 1143 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
1128 1144 return (EINVAL);
1129 1145
1130 1146 case NVME_CQE_SC_SPC_INV_FORMAT:
1131 1147 /* Invalid Format */
1132 1148 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
1133 1149 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
1134 1150 if (cmd->nc_xfer != NULL)
1135 1151 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1136 1152 return (EINVAL);
1137 1153
1138 1154 case NVME_CQE_SC_SPC_INV_Q_DEL:
1139 1155 /* Invalid Queue Deletion */
1140 1156 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1141 1157 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
1142 1158 return (EINVAL);
1143 1159
1144 1160 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
1145 1161 /* Conflicting Attributes */
1146 1162 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
1147 1163 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1148 1164 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1149 1165 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
1150 1166 if (cmd->nc_xfer != NULL)
1151 1167 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1152 1168 return (EINVAL);
1153 1169
1154 1170 case NVME_CQE_SC_SPC_NVM_INV_PROT:
1155 1171 /* Invalid Protection Information */
1156 1172 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1157 1173 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1158 1174 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1159 1175 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1160 1176 if (cmd->nc_xfer != NULL)
1161 1177 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1162 1178 return (EINVAL);
1163 1179
1164 1180 case NVME_CQE_SC_SPC_NVM_READONLY:
1165 1181 /* Write to Read Only Range */
1166 1182 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1167 1183 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1168 1184 if (cmd->nc_xfer != NULL)
1169 1185 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1170 1186 return (EROFS);
1171 1187
1172 1188 default:
1173 1189 return (nvme_check_unknown_cmd_status(cmd));
1174 1190 }
1175 1191 }
1176 1192
1177 1193 static inline int
1178 1194 nvme_check_cmd_status(nvme_cmd_t *cmd)
1179 1195 {
1180 1196 nvme_cqe_t *cqe = &cmd->nc_cqe;
1181 1197
1182 1198 /* take a shortcut if everything is alright */
1183 1199 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1184 1200 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1185 1201 return (0);
1186 1202
1187 1203 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1188 1204 return (nvme_check_generic_cmd_status(cmd));
1189 1205 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1190 1206 return (nvme_check_specific_cmd_status(cmd));
1191 1207 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1192 1208 return (nvme_check_integrity_cmd_status(cmd));
1193 1209 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1194 1210 return (nvme_check_vendor_cmd_status(cmd));
1195 1211
1196 1212 return (nvme_check_unknown_cmd_status(cmd));
1197 1213 }
1198 1214
1199 1215 /*
1200 1216 * nvme_abort_cmd_cb -- replaces nc_callback of aborted commands
1201 1217 *
1202 1218 * This functions takes care of cleaning up aborted commands. The command
1203 1219 * status is checked to catch any fatal errors.
1204 1220 */
1205 1221 static void
1206 1222 nvme_abort_cmd_cb(void *arg)
1207 1223 {
1208 1224 nvme_cmd_t *cmd = arg;
1209 1225
1210 1226 /*
1211 1227 * Grab the command mutex. Once we have it we hold the last reference
1212 1228 * to the command and can safely free it.
1213 1229 */
1214 1230 mutex_enter(&cmd->nc_mutex);
1215 1231 (void) nvme_check_cmd_status(cmd);
1216 1232 mutex_exit(&cmd->nc_mutex);
1217 1233
1218 1234 nvme_free_cmd(cmd);
1219 1235 }
1220 1236
1221 1237 static void
1222 1238 nvme_abort_cmd(nvme_cmd_t *abort_cmd)
1223 1239 {
1224 1240 nvme_t *nvme = abort_cmd->nc_nvme;
1225 1241 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1226 1242 nvme_abort_cmd_t ac = { 0 };
1227 1243
1228 1244 sema_p(&nvme->n_abort_sema);
1229 1245
1230 1246 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1231 1247 ac.b.ac_sqid = abort_cmd->nc_sqid;
1232 1248
1233 1249 /*
1234 1250 * Drop the mutex of the aborted command. From this point on
1235 1251 * we must assume that the abort callback has freed the command.
1236 1252 */
1237 1253 mutex_exit(&abort_cmd->nc_mutex);
1238 1254
1239 1255 cmd->nc_sqid = 0;
1240 1256 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1241 1257 cmd->nc_callback = nvme_wakeup_cmd;
1242 1258 cmd->nc_sqe.sqe_cdw10 = ac.r;
1243 1259
1244 1260 /*
1245 1261 * Send the ABORT to the hardware. The ABORT command will return _after_
1246 1262 * the aborted command has completed (aborted or otherwise).
1247 1263 */
1248 1264 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1249 1265 sema_v(&nvme->n_abort_sema);
1250 1266 dev_err(nvme->n_dip, CE_WARN,
1251 1267 "!nvme_admin_cmd failed for ABORT");
1252 1268 atomic_inc_32(&nvme->n_abort_failed);
1253 1269 return;
1254 1270 }
1255 1271 sema_v(&nvme->n_abort_sema);
1256 1272
1257 1273 if (nvme_check_cmd_status(cmd)) {
1258 1274 dev_err(nvme->n_dip, CE_WARN,
1259 1275 "!ABORT failed with sct = %x, sc = %x",
1260 1276 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1261 1277 atomic_inc_32(&nvme->n_abort_failed);
1262 1278 } else {
1263 1279 atomic_inc_32(&nvme->n_cmd_aborted);
1264 1280 }
1265 1281
1266 1282 nvme_free_cmd(cmd);
1267 1283 }
1268 1284
1269 1285 /*
1270 1286 * nvme_wait_cmd -- wait for command completion or timeout
1271 1287 *
1272 1288 * Returns B_TRUE if the command completed normally.
1273 1289 *
1274 1290 * Returns B_FALSE if the command timed out and an abort was attempted. The
1275 1291 * command mutex will be dropped and the command must be considered freed. The
1276 1292 * freeing of the command is normally done by the abort command callback.
1277 1293 *
1278 1294 * In case of a serious error or a timeout of the abort command the hardware
1279 1295 * will be declared dead and FMA will be notified.
1280 1296 */
1281 1297 static boolean_t
1282 1298 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1283 1299 {
1284 1300 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1285 1301 nvme_t *nvme = cmd->nc_nvme;
1286 1302 nvme_reg_csts_t csts;
1287 1303
1288 1304 ASSERT(mutex_owned(&cmd->nc_mutex));
1289 1305
1290 1306 while (!cmd->nc_completed) {
1291 1307 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1292 1308 break;
1293 1309 }
1294 1310
1295 1311 if (cmd->nc_completed)
1296 1312 return (B_TRUE);
1297 1313
1298 1314 /*
1299 1315 * The command timed out. Change the callback to the cleanup function.
1300 1316 */
1301 1317 cmd->nc_callback = nvme_abort_cmd_cb;
1302 1318
1303 1319 /*
1304 1320 * Check controller for fatal status, any errors associated with the
1305 1321 * register or DMA handle, or for a double timeout (abort command timed
1306 1322 * out). If necessary log a warning and call FMA.
1307 1323 */
1308 1324 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1309 1325 dev_err(nvme->n_dip, CE_WARN, "!command timeout, "
1310 1326 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1311 1327 atomic_inc_32(&nvme->n_cmd_timeout);
1312 1328
1313 1329 if (csts.b.csts_cfs ||
1314 1330 nvme_check_regs_hdl(nvme) ||
1315 1331 nvme_check_dma_hdl(cmd->nc_dma) ||
1316 1332 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1317 1333 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1318 1334 nvme->n_dead = B_TRUE;
1319 1335 mutex_exit(&cmd->nc_mutex);
1320 1336 } else {
1321 1337 /*
1322 1338 * Try to abort the command. The command mutex is released by
1323 1339 * nvme_abort_cmd().
1324 1340 * If the abort succeeds it will have freed the aborted command.
1325 1341 * If the abort fails for other reasons we must assume that the
1326 1342 * command may complete at any time, and the callback will free
1327 1343 * it for us.
1328 1344 */
1329 1345 nvme_abort_cmd(cmd);
1330 1346 }
1331 1347
1332 1348 return (B_FALSE);
1333 1349 }
1334 1350
1335 1351 static void
1336 1352 nvme_wakeup_cmd(void *arg)
1337 1353 {
1338 1354 nvme_cmd_t *cmd = arg;
1339 1355
1340 1356 mutex_enter(&cmd->nc_mutex);
1341 1357 /*
1342 1358 * There is a slight chance that this command completed shortly after
1343 1359 * the timeout was hit in nvme_wait_cmd() but before the callback was
1344 1360 * changed. Catch that case here and clean up accordingly.
1345 1361 */
1346 1362 if (cmd->nc_callback == nvme_abort_cmd_cb) {
1347 1363 mutex_exit(&cmd->nc_mutex);
1348 1364 nvme_abort_cmd_cb(cmd);
1349 1365 return;
1350 1366 }
1351 1367
1352 1368 cmd->nc_completed = B_TRUE;
1353 1369 cv_signal(&cmd->nc_cv);
1354 1370 mutex_exit(&cmd->nc_mutex);
1355 1371 }
↓ open down ↓ |
448 lines elided |
↑ open up ↑ |
1356 1372
1357 1373 static void
1358 1374 nvme_async_event_task(void *arg)
1359 1375 {
1360 1376 nvme_cmd_t *cmd = arg;
1361 1377 nvme_t *nvme = cmd->nc_nvme;
1362 1378 nvme_error_log_entry_t *error_log = NULL;
1363 1379 nvme_health_log_t *health_log = NULL;
1364 1380 size_t logsize = 0;
1365 1381 nvme_async_event_t event;
1366 - int ret;
1367 1382
1368 1383 /*
1369 1384 * Check for errors associated with the async request itself. The only
1370 1385 * command-specific error is "async event limit exceeded", which
1371 1386 * indicates a programming error in the driver and causes a panic in
1372 1387 * nvme_check_cmd_status().
1373 1388 *
1374 1389 * Other possible errors are various scenarios where the async request
1375 1390 * was aborted, or internal errors in the device. Internal errors are
1376 1391 * reported to FMA, the command aborts need no special handling here.
1377 1392 */
1378 1393 if (nvme_check_cmd_status(cmd)) {
1379 1394 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1380 1395 "!async event request returned failure, sct = %x, "
1381 1396 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1382 1397 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1383 1398 cmd->nc_cqe.cqe_sf.sf_m);
1384 1399
1385 1400 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1386 1401 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1387 1402 cmd->nc_nvme->n_dead = B_TRUE;
1388 1403 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1389 1404 DDI_SERVICE_LOST);
↓ open down ↓ |
13 lines elided |
↑ open up ↑ |
1390 1405 }
1391 1406 nvme_free_cmd(cmd);
1392 1407 return;
1393 1408 }
1394 1409
1395 1410
1396 1411 event.r = cmd->nc_cqe.cqe_dw0;
1397 1412
1398 1413 /* Clear CQE and re-submit the async request. */
1399 1414 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1400 - ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1415 + nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1401 1416
1402 - if (ret != DDI_SUCCESS) {
1403 - dev_err(nvme->n_dip, CE_WARN,
1404 - "!failed to resubmit async event request");
1405 - atomic_inc_32(&nvme->n_async_resubmit_failed);
1406 - nvme_free_cmd(cmd);
1407 - }
1408 -
1409 1417 switch (event.b.ae_type) {
1410 1418 case NVME_ASYNC_TYPE_ERROR:
1411 1419 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1412 1420 (void) nvme_get_logpage(nvme, (void **)&error_log,
1413 1421 &logsize, event.b.ae_logpage);
1414 1422 } else {
1415 1423 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1416 1424 "async event reply: %d", event.b.ae_logpage);
1417 1425 atomic_inc_32(&nvme->n_wrong_logpage);
1418 1426 }
1419 1427
1420 1428 switch (event.b.ae_info) {
1421 1429 case NVME_ASYNC_ERROR_INV_SQ:
1422 1430 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1423 1431 "invalid submission queue");
1424 1432 return;
1425 1433
1426 1434 case NVME_ASYNC_ERROR_INV_DBL:
1427 1435 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1428 1436 "invalid doorbell write value");
1429 1437 return;
1430 1438
1431 1439 case NVME_ASYNC_ERROR_DIAGFAIL:
1432 1440 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1433 1441 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1434 1442 nvme->n_dead = B_TRUE;
1435 1443 atomic_inc_32(&nvme->n_diagfail_event);
1436 1444 break;
1437 1445
1438 1446 case NVME_ASYNC_ERROR_PERSISTENT:
1439 1447 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1440 1448 "device error");
1441 1449 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1442 1450 nvme->n_dead = B_TRUE;
1443 1451 atomic_inc_32(&nvme->n_persistent_event);
1444 1452 break;
1445 1453
1446 1454 case NVME_ASYNC_ERROR_TRANSIENT:
1447 1455 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1448 1456 "device error");
1449 1457 /* TODO: send ereport */
1450 1458 atomic_inc_32(&nvme->n_transient_event);
1451 1459 break;
1452 1460
1453 1461 case NVME_ASYNC_ERROR_FW_LOAD:
1454 1462 dev_err(nvme->n_dip, CE_WARN,
1455 1463 "!firmware image load error");
1456 1464 atomic_inc_32(&nvme->n_fw_load_event);
1457 1465 break;
1458 1466 }
1459 1467 break;
1460 1468
1461 1469 case NVME_ASYNC_TYPE_HEALTH:
1462 1470 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1463 1471 (void) nvme_get_logpage(nvme, (void **)&health_log,
1464 1472 &logsize, event.b.ae_logpage, -1);
1465 1473 } else {
1466 1474 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1467 1475 "async event reply: %d", event.b.ae_logpage);
1468 1476 atomic_inc_32(&nvme->n_wrong_logpage);
1469 1477 }
1470 1478
1471 1479 switch (event.b.ae_info) {
1472 1480 case NVME_ASYNC_HEALTH_RELIABILITY:
1473 1481 dev_err(nvme->n_dip, CE_WARN,
1474 1482 "!device reliability compromised");
1475 1483 /* TODO: send ereport */
1476 1484 atomic_inc_32(&nvme->n_reliability_event);
1477 1485 break;
1478 1486
1479 1487 case NVME_ASYNC_HEALTH_TEMPERATURE:
1480 1488 dev_err(nvme->n_dip, CE_WARN,
1481 1489 "!temperature above threshold");
1482 1490 /* TODO: send ereport */
1483 1491 atomic_inc_32(&nvme->n_temperature_event);
1484 1492 break;
1485 1493
1486 1494 case NVME_ASYNC_HEALTH_SPARE:
1487 1495 dev_err(nvme->n_dip, CE_WARN,
1488 1496 "!spare space below threshold");
1489 1497 /* TODO: send ereport */
1490 1498 atomic_inc_32(&nvme->n_spare_event);
1491 1499 break;
1492 1500 }
1493 1501 break;
1494 1502
1495 1503 case NVME_ASYNC_TYPE_VENDOR:
1496 1504 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1497 1505 "received, info = %x, logpage = %x", event.b.ae_info,
1498 1506 event.b.ae_logpage);
1499 1507 atomic_inc_32(&nvme->n_vendor_event);
1500 1508 break;
1501 1509
1502 1510 default:
1503 1511 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1504 1512 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1505 1513 event.b.ae_info, event.b.ae_logpage);
1506 1514 atomic_inc_32(&nvme->n_unknown_event);
1507 1515 break;
1508 1516 }
1509 1517
↓ open down ↓ |
91 lines elided |
↑ open up ↑ |
1510 1518 if (error_log)
1511 1519 kmem_free(error_log, logsize);
1512 1520
1513 1521 if (health_log)
1514 1522 kmem_free(health_log, logsize);
1515 1523 }
1516 1524
1517 1525 static int
1518 1526 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1519 1527 {
1520 - int ret;
1521 -
1522 1528 mutex_enter(&cmd->nc_mutex);
1523 - ret = nvme_submit_cmd(cmd->nc_nvme->n_adminq, cmd);
1529 + nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd);
1524 1530
1525 - if (ret != DDI_SUCCESS) {
1526 - mutex_exit(&cmd->nc_mutex);
1527 - dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1528 - "!nvme_submit_cmd failed");
1529 - atomic_inc_32(&cmd->nc_nvme->n_admin_queue_full);
1530 - nvme_free_cmd(cmd);
1531 - return (DDI_FAILURE);
1532 - }
1533 -
1534 1531 if (nvme_wait_cmd(cmd, sec) == B_FALSE) {
1535 1532 /*
1536 1533 * The command timed out. An abort command was posted that
1537 1534 * will take care of the cleanup.
1538 1535 */
1539 1536 return (DDI_FAILURE);
1540 1537 }
1541 1538 mutex_exit(&cmd->nc_mutex);
1542 1539
1543 1540 return (DDI_SUCCESS);
1544 1541 }
1545 1542
1546 -static int
1543 +static void
1547 1544 nvme_async_event(nvme_t *nvme)
1548 1545 {
1549 1546 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1550 - int ret;
1551 1547
1552 1548 cmd->nc_sqid = 0;
1553 1549 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1554 1550 cmd->nc_callback = nvme_async_event_task;
1555 1551
1556 - ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1557 -
1558 - if (ret != DDI_SUCCESS) {
1559 - dev_err(nvme->n_dip, CE_WARN,
1560 - "!nvme_submit_cmd failed for ASYNCHRONOUS EVENT");
1561 - nvme_free_cmd(cmd);
1562 - return (DDI_FAILURE);
1563 - }
1564 -
1565 - return (DDI_SUCCESS);
1552 + nvme_submit_admin_cmd(nvme->n_adminq, cmd);
1566 1553 }
1567 1554
1568 1555 static int
1569 1556 nvme_format_nvm(nvme_t *nvme, uint32_t nsid, uint8_t lbaf, boolean_t ms,
1570 1557 uint8_t pi, boolean_t pil, uint8_t ses)
1571 1558 {
1572 1559 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1573 1560 nvme_format_nvm_t format_nvm = { 0 };
1574 1561 int ret;
1575 1562
1576 1563 format_nvm.b.fm_lbaf = lbaf & 0xf;
1577 1564 format_nvm.b.fm_ms = ms ? 1 : 0;
1578 1565 format_nvm.b.fm_pi = pi & 0x7;
1579 1566 format_nvm.b.fm_pil = pil ? 1 : 0;
1580 1567 format_nvm.b.fm_ses = ses & 0x7;
1581 1568
1582 1569 cmd->nc_sqid = 0;
1583 1570 cmd->nc_callback = nvme_wakeup_cmd;
1584 1571 cmd->nc_sqe.sqe_nsid = nsid;
1585 1572 cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT;
1586 1573 cmd->nc_sqe.sqe_cdw10 = format_nvm.r;
1587 1574
1588 1575 /*
1589 1576 * Some devices like Samsung SM951 don't allow formatting of all
1590 1577 * namespaces in one command. Handle that gracefully.
1591 1578 */
1592 1579 if (nsid == (uint32_t)-1)
1593 1580 cmd->nc_dontpanic = B_TRUE;
1594 1581
1595 1582 if ((ret = nvme_admin_cmd(cmd, nvme_format_cmd_timeout))
1596 1583 != DDI_SUCCESS) {
1597 1584 dev_err(nvme->n_dip, CE_WARN,
1598 1585 "!nvme_admin_cmd failed for FORMAT NVM");
1599 1586 return (EIO);
1600 1587 }
1601 1588
1602 1589 if ((ret = nvme_check_cmd_status(cmd)) != 0) {
1603 1590 dev_err(nvme->n_dip, CE_WARN,
1604 1591 "!FORMAT failed with sct = %x, sc = %x",
1605 1592 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1606 1593 }
1607 1594
1608 1595 nvme_free_cmd(cmd);
1609 1596 return (ret);
1610 1597 }
1611 1598
1612 1599 static int
1613 1600 nvme_get_logpage(nvme_t *nvme, void **buf, size_t *bufsize, uint8_t logpage,
1614 1601 ...)
1615 1602 {
1616 1603 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1617 1604 nvme_getlogpage_t getlogpage = { 0 };
1618 1605 va_list ap;
1619 1606 int ret = DDI_FAILURE;
1620 1607
1621 1608 va_start(ap, logpage);
1622 1609
1623 1610 cmd->nc_sqid = 0;
1624 1611 cmd->nc_callback = nvme_wakeup_cmd;
1625 1612 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1626 1613
1627 1614 getlogpage.b.lp_lid = logpage;
1628 1615
1629 1616 switch (logpage) {
1630 1617 case NVME_LOGPAGE_ERROR:
1631 1618 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1632 1619 /*
1633 1620 * The GET LOG PAGE command can use at most 2 pages to return
1634 1621 * data, PRP lists are not supported.
1635 1622 */
1636 1623 *bufsize = MIN(2 * nvme->n_pagesize,
1637 1624 nvme->n_error_log_len * sizeof (nvme_error_log_entry_t));
1638 1625 break;
1639 1626
1640 1627 case NVME_LOGPAGE_HEALTH:
1641 1628 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1642 1629 *bufsize = sizeof (nvme_health_log_t);
1643 1630 break;
1644 1631
1645 1632 case NVME_LOGPAGE_FWSLOT:
1646 1633 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1647 1634 *bufsize = sizeof (nvme_fwslot_log_t);
1648 1635 break;
1649 1636
1650 1637 default:
1651 1638 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1652 1639 logpage);
1653 1640 atomic_inc_32(&nvme->n_unknown_logpage);
1654 1641 goto fail;
1655 1642 }
1656 1643
1657 1644 va_end(ap);
1658 1645
1659 1646 getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1;
1660 1647
1661 1648 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1662 1649
1663 1650 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1664 1651 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1665 1652 dev_err(nvme->n_dip, CE_WARN,
1666 1653 "!nvme_zalloc_dma failed for GET LOG PAGE");
1667 1654 goto fail;
1668 1655 }
1669 1656
1670 1657 if (cmd->nc_dma->nd_ncookie > 2) {
1671 1658 dev_err(nvme->n_dip, CE_WARN,
1672 1659 "!too many DMA cookies for GET LOG PAGE");
1673 1660 atomic_inc_32(&nvme->n_too_many_cookies);
1674 1661 goto fail;
1675 1662 }
1676 1663
1677 1664 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1678 1665 if (cmd->nc_dma->nd_ncookie > 1) {
1679 1666 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1680 1667 &cmd->nc_dma->nd_cookie);
1681 1668 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1682 1669 cmd->nc_dma->nd_cookie.dmac_laddress;
1683 1670 }
1684 1671
1685 1672 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1686 1673 dev_err(nvme->n_dip, CE_WARN,
1687 1674 "!nvme_admin_cmd failed for GET LOG PAGE");
1688 1675 return (ret);
1689 1676 }
1690 1677
1691 1678 if (nvme_check_cmd_status(cmd)) {
1692 1679 dev_err(nvme->n_dip, CE_WARN,
1693 1680 "!GET LOG PAGE failed with sct = %x, sc = %x",
1694 1681 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1695 1682 goto fail;
1696 1683 }
1697 1684
1698 1685 *buf = kmem_alloc(*bufsize, KM_SLEEP);
1699 1686 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
1700 1687
1701 1688 ret = DDI_SUCCESS;
1702 1689
1703 1690 fail:
1704 1691 nvme_free_cmd(cmd);
1705 1692
1706 1693 return (ret);
1707 1694 }
1708 1695
1709 1696 static void *
1710 1697 nvme_identify(nvme_t *nvme, uint32_t nsid)
1711 1698 {
1712 1699 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1713 1700 void *buf = NULL;
1714 1701
1715 1702 cmd->nc_sqid = 0;
1716 1703 cmd->nc_callback = nvme_wakeup_cmd;
1717 1704 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1718 1705 cmd->nc_sqe.sqe_nsid = nsid;
1719 1706 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1720 1707
1721 1708 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1722 1709 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1723 1710 dev_err(nvme->n_dip, CE_WARN,
1724 1711 "!nvme_zalloc_dma failed for IDENTIFY");
1725 1712 goto fail;
1726 1713 }
1727 1714
1728 1715 if (cmd->nc_dma->nd_ncookie > 2) {
1729 1716 dev_err(nvme->n_dip, CE_WARN,
1730 1717 "!too many DMA cookies for IDENTIFY");
1731 1718 atomic_inc_32(&nvme->n_too_many_cookies);
1732 1719 goto fail;
1733 1720 }
1734 1721
1735 1722 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1736 1723 if (cmd->nc_dma->nd_ncookie > 1) {
1737 1724 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1738 1725 &cmd->nc_dma->nd_cookie);
1739 1726 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1740 1727 cmd->nc_dma->nd_cookie.dmac_laddress;
1741 1728 }
1742 1729
1743 1730 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1744 1731 dev_err(nvme->n_dip, CE_WARN,
1745 1732 "!nvme_admin_cmd failed for IDENTIFY");
1746 1733 return (NULL);
1747 1734 }
1748 1735
1749 1736 if (nvme_check_cmd_status(cmd)) {
1750 1737 dev_err(nvme->n_dip, CE_WARN,
1751 1738 "!IDENTIFY failed with sct = %x, sc = %x",
1752 1739 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1753 1740 goto fail;
1754 1741 }
1755 1742
1756 1743 buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1757 1744 bcopy(cmd->nc_dma->nd_memp, buf, NVME_IDENTIFY_BUFSIZE);
1758 1745
1759 1746 fail:
1760 1747 nvme_free_cmd(cmd);
1761 1748
1762 1749 return (buf);
1763 1750 }
1764 1751
1765 1752 static boolean_t
1766 1753 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val,
1767 1754 uint32_t *res)
1768 1755 {
1769 1756 _NOTE(ARGUNUSED(nsid));
1770 1757 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1771 1758 boolean_t ret = B_FALSE;
1772 1759
1773 1760 ASSERT(res != NULL);
1774 1761
1775 1762 cmd->nc_sqid = 0;
1776 1763 cmd->nc_callback = nvme_wakeup_cmd;
1777 1764 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1778 1765 cmd->nc_sqe.sqe_cdw10 = feature;
1779 1766 cmd->nc_sqe.sqe_cdw11 = val;
1780 1767
1781 1768 switch (feature) {
1782 1769 case NVME_FEAT_WRITE_CACHE:
1783 1770 if (!nvme->n_write_cache_present)
1784 1771 goto fail;
1785 1772 break;
1786 1773
1787 1774 case NVME_FEAT_NQUEUES:
1788 1775 break;
1789 1776
1790 1777 default:
1791 1778 goto fail;
1792 1779 }
1793 1780
1794 1781 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1795 1782 dev_err(nvme->n_dip, CE_WARN,
1796 1783 "!nvme_admin_cmd failed for SET FEATURES");
1797 1784 return (ret);
1798 1785 }
1799 1786
1800 1787 if (nvme_check_cmd_status(cmd)) {
1801 1788 dev_err(nvme->n_dip, CE_WARN,
1802 1789 "!SET FEATURES %d failed with sct = %x, sc = %x",
1803 1790 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1804 1791 cmd->nc_cqe.cqe_sf.sf_sc);
1805 1792 goto fail;
1806 1793 }
1807 1794
1808 1795 *res = cmd->nc_cqe.cqe_dw0;
1809 1796 ret = B_TRUE;
1810 1797
1811 1798 fail:
1812 1799 nvme_free_cmd(cmd);
1813 1800 return (ret);
1814 1801 }
1815 1802
1816 1803 static boolean_t
1817 1804 nvme_get_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t *res,
1818 1805 void **buf, size_t *bufsize)
1819 1806 {
1820 1807 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1821 1808 boolean_t ret = B_FALSE;
1822 1809
1823 1810 ASSERT(res != NULL);
1824 1811
1825 1812 if (bufsize != NULL)
1826 1813 *bufsize = 0;
1827 1814
1828 1815 cmd->nc_sqid = 0;
1829 1816 cmd->nc_callback = nvme_wakeup_cmd;
1830 1817 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES;
1831 1818 cmd->nc_sqe.sqe_cdw10 = feature;
1832 1819 cmd->nc_sqe.sqe_cdw11 = *res;
1833 1820
1834 1821 switch (feature) {
1835 1822 case NVME_FEAT_ARBITRATION:
1836 1823 case NVME_FEAT_POWER_MGMT:
1837 1824 case NVME_FEAT_TEMPERATURE:
1838 1825 case NVME_FEAT_ERROR:
1839 1826 case NVME_FEAT_NQUEUES:
1840 1827 case NVME_FEAT_INTR_COAL:
1841 1828 case NVME_FEAT_INTR_VECT:
1842 1829 case NVME_FEAT_WRITE_ATOM:
1843 1830 case NVME_FEAT_ASYNC_EVENT:
1844 1831 case NVME_FEAT_PROGRESS:
1845 1832 break;
1846 1833
1847 1834 case NVME_FEAT_WRITE_CACHE:
1848 1835 if (!nvme->n_write_cache_present)
1849 1836 goto fail;
1850 1837 break;
1851 1838
1852 1839 case NVME_FEAT_LBA_RANGE:
1853 1840 if (!nvme->n_lba_range_supported)
1854 1841 goto fail;
1855 1842
1856 1843 /*
1857 1844 * The LBA Range Type feature is optional. There doesn't seem
1858 1845 * be a method of detecting whether it is supported other than
1859 1846 * using it. This will cause a "invalid field in command" error,
1860 1847 * which is normally considered a programming error and causes
1861 1848 * panic in nvme_check_generic_cmd_status().
1862 1849 */
1863 1850 cmd->nc_dontpanic = B_TRUE;
1864 1851 cmd->nc_sqe.sqe_nsid = nsid;
1865 1852 ASSERT(bufsize != NULL);
1866 1853 *bufsize = NVME_LBA_RANGE_BUFSIZE;
1867 1854
1868 1855 break;
1869 1856
1870 1857 case NVME_FEAT_AUTO_PST:
1871 1858 if (!nvme->n_auto_pst_supported)
1872 1859 goto fail;
1873 1860
1874 1861 ASSERT(bufsize != NULL);
1875 1862 *bufsize = NVME_AUTO_PST_BUFSIZE;
1876 1863 break;
1877 1864
1878 1865 default:
1879 1866 goto fail;
1880 1867 }
1881 1868
1882 1869 if (bufsize != NULL && *bufsize != 0) {
1883 1870 if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ,
1884 1871 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1885 1872 dev_err(nvme->n_dip, CE_WARN,
1886 1873 "!nvme_zalloc_dma failed for GET FEATURES");
1887 1874 goto fail;
1888 1875 }
1889 1876
1890 1877 if (cmd->nc_dma->nd_ncookie > 2) {
1891 1878 dev_err(nvme->n_dip, CE_WARN,
1892 1879 "!too many DMA cookies for GET FEATURES");
1893 1880 atomic_inc_32(&nvme->n_too_many_cookies);
1894 1881 goto fail;
1895 1882 }
1896 1883
1897 1884 cmd->nc_sqe.sqe_dptr.d_prp[0] =
1898 1885 cmd->nc_dma->nd_cookie.dmac_laddress;
1899 1886 if (cmd->nc_dma->nd_ncookie > 1) {
1900 1887 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1901 1888 &cmd->nc_dma->nd_cookie);
1902 1889 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1903 1890 cmd->nc_dma->nd_cookie.dmac_laddress;
1904 1891 }
1905 1892 }
1906 1893
1907 1894 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1908 1895 dev_err(nvme->n_dip, CE_WARN,
1909 1896 "!nvme_admin_cmd failed for GET FEATURES");
1910 1897 return (ret);
1911 1898 }
1912 1899
1913 1900 if (nvme_check_cmd_status(cmd)) {
1914 1901 if (feature == NVME_FEAT_LBA_RANGE &&
1915 1902 cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1916 1903 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD)
1917 1904 nvme->n_lba_range_supported = B_FALSE;
1918 1905 else
1919 1906 dev_err(nvme->n_dip, CE_WARN,
1920 1907 "!GET FEATURES %d failed with sct = %x, sc = %x",
1921 1908 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1922 1909 cmd->nc_cqe.cqe_sf.sf_sc);
1923 1910 goto fail;
1924 1911 }
1925 1912
1926 1913 if (bufsize != NULL && *bufsize != 0) {
1927 1914 ASSERT(buf != NULL);
1928 1915 *buf = kmem_alloc(*bufsize, KM_SLEEP);
1929 1916 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
1930 1917 }
1931 1918
1932 1919 *res = cmd->nc_cqe.cqe_dw0;
1933 1920 ret = B_TRUE;
1934 1921
1935 1922 fail:
1936 1923 nvme_free_cmd(cmd);
1937 1924 return (ret);
1938 1925 }
1939 1926
1940 1927 static boolean_t
1941 1928 nvme_write_cache_set(nvme_t *nvme, boolean_t enable)
1942 1929 {
1943 1930 nvme_write_cache_t nwc = { 0 };
1944 1931
1945 1932 if (enable)
1946 1933 nwc.b.wc_wce = 1;
1947 1934
1948 1935 if (!nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r, &nwc.r))
1949 1936 return (B_FALSE);
1950 1937
1951 1938 return (B_TRUE);
1952 1939 }
1953 1940
1954 1941 static int
1955 1942 nvme_set_nqueues(nvme_t *nvme, uint16_t nqueues)
1956 1943 {
1957 1944 nvme_nqueues_t nq = { 0 };
1958 1945
1959 1946 nq.b.nq_nsq = nq.b.nq_ncq = nqueues - 1;
1960 1947
1961 1948 if (!nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r)) {
1962 1949 return (0);
1963 1950 }
1964 1951
1965 1952 /*
1966 1953 * Always use the same number of submission and completion queues, and
1967 1954 * never use more than the requested number of queues.
1968 1955 */
1969 1956 return (MIN(nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1));
1970 1957 }
1971 1958
1972 1959 static int
1973 1960 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
1974 1961 {
1975 1962 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1976 1963 nvme_create_queue_dw10_t dw10 = { 0 };
1977 1964 nvme_create_cq_dw11_t c_dw11 = { 0 };
1978 1965 nvme_create_sq_dw11_t s_dw11 = { 0 };
1979 1966
1980 1967 dw10.b.q_qid = idx;
1981 1968 dw10.b.q_qsize = qp->nq_nentry - 1;
1982 1969
1983 1970 c_dw11.b.cq_pc = 1;
1984 1971 c_dw11.b.cq_ien = 1;
1985 1972 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
1986 1973
1987 1974 cmd->nc_sqid = 0;
1988 1975 cmd->nc_callback = nvme_wakeup_cmd;
1989 1976 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
1990 1977 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1991 1978 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
1992 1979 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
1993 1980
1994 1981 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1995 1982 dev_err(nvme->n_dip, CE_WARN,
1996 1983 "!nvme_admin_cmd failed for CREATE CQUEUE");
1997 1984 return (DDI_FAILURE);
1998 1985 }
1999 1986
2000 1987 if (nvme_check_cmd_status(cmd)) {
2001 1988 dev_err(nvme->n_dip, CE_WARN,
2002 1989 "!CREATE CQUEUE failed with sct = %x, sc = %x",
2003 1990 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2004 1991 nvme_free_cmd(cmd);
2005 1992 return (DDI_FAILURE);
2006 1993 }
2007 1994
2008 1995 nvme_free_cmd(cmd);
2009 1996
2010 1997 s_dw11.b.sq_pc = 1;
2011 1998 s_dw11.b.sq_cqid = idx;
2012 1999
2013 2000 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
2014 2001 cmd->nc_sqid = 0;
2015 2002 cmd->nc_callback = nvme_wakeup_cmd;
2016 2003 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
2017 2004 cmd->nc_sqe.sqe_cdw10 = dw10.r;
2018 2005 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
2019 2006 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
2020 2007
2021 2008 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
2022 2009 dev_err(nvme->n_dip, CE_WARN,
2023 2010 "!nvme_admin_cmd failed for CREATE SQUEUE");
2024 2011 return (DDI_FAILURE);
2025 2012 }
2026 2013
2027 2014 if (nvme_check_cmd_status(cmd)) {
2028 2015 dev_err(nvme->n_dip, CE_WARN,
2029 2016 "!CREATE SQUEUE failed with sct = %x, sc = %x",
2030 2017 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
2031 2018 nvme_free_cmd(cmd);
2032 2019 return (DDI_FAILURE);
2033 2020 }
2034 2021
2035 2022 nvme_free_cmd(cmd);
2036 2023
2037 2024 return (DDI_SUCCESS);
2038 2025 }
2039 2026
2040 2027 static boolean_t
2041 2028 nvme_reset(nvme_t *nvme, boolean_t quiesce)
2042 2029 {
2043 2030 nvme_reg_csts_t csts;
2044 2031 int i;
2045 2032
2046 2033 nvme_put32(nvme, NVME_REG_CC, 0);
2047 2034
2048 2035 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2049 2036 if (csts.b.csts_rdy == 1) {
2050 2037 nvme_put32(nvme, NVME_REG_CC, 0);
2051 2038 for (i = 0; i != nvme->n_timeout * 10; i++) {
2052 2039 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2053 2040 if (csts.b.csts_rdy == 0)
2054 2041 break;
2055 2042
2056 2043 if (quiesce)
2057 2044 drv_usecwait(50000);
2058 2045 else
2059 2046 delay(drv_usectohz(50000));
2060 2047 }
2061 2048 }
2062 2049
2063 2050 nvme_put32(nvme, NVME_REG_AQA, 0);
2064 2051 nvme_put32(nvme, NVME_REG_ASQ, 0);
2065 2052 nvme_put32(nvme, NVME_REG_ACQ, 0);
2066 2053
2067 2054 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2068 2055 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
2069 2056 }
2070 2057
2071 2058 static void
2072 2059 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
2073 2060 {
2074 2061 nvme_reg_cc_t cc;
2075 2062 nvme_reg_csts_t csts;
2076 2063 int i;
2077 2064
2078 2065 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
2079 2066
2080 2067 cc.r = nvme_get32(nvme, NVME_REG_CC);
2081 2068 cc.b.cc_shn = mode & 0x3;
2082 2069 nvme_put32(nvme, NVME_REG_CC, cc.r);
2083 2070
2084 2071 for (i = 0; i != 10; i++) {
2085 2072 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2086 2073 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
2087 2074 break;
2088 2075
2089 2076 if (quiesce)
2090 2077 drv_usecwait(100000);
2091 2078 else
2092 2079 delay(drv_usectohz(100000));
2093 2080 }
2094 2081 }
2095 2082
2096 2083
2097 2084 static void
2098 2085 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
2099 2086 {
2100 2087 /*
2101 2088 * Section 7.7 of the spec describes how to get a unique ID for
2102 2089 * the controller: the vendor ID, the model name and the serial
2103 2090 * number shall be unique when combined.
2104 2091 *
2105 2092 * If a namespace has no EUI64 we use the above and add the hex
2106 2093 * namespace ID to get a unique ID for the namespace.
2107 2094 */
2108 2095 char model[sizeof (nvme->n_idctl->id_model) + 1];
2109 2096 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
2110 2097
2111 2098 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2112 2099 bcopy(nvme->n_idctl->id_serial, serial,
2113 2100 sizeof (nvme->n_idctl->id_serial));
2114 2101
2115 2102 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2116 2103 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
2117 2104
2118 2105 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X",
2119 2106 nvme->n_idctl->id_vid, model, serial, nsid);
2120 2107 }
2121 2108
2122 2109 static int
2123 2110 nvme_init_ns(nvme_t *nvme, int nsid)
2124 2111 {
2125 2112 nvme_namespace_t *ns = &nvme->n_ns[nsid - 1];
2126 2113 nvme_identify_nsid_t *idns;
2127 2114 int last_rp;
2128 2115
2129 2116 ns->ns_nvme = nvme;
2130 2117 idns = nvme_identify(nvme, nsid);
2131 2118
2132 2119 if (idns == NULL) {
2133 2120 dev_err(nvme->n_dip, CE_WARN,
2134 2121 "!failed to identify namespace %d", nsid);
2135 2122 return (DDI_FAILURE);
2136 2123 }
2137 2124
2138 2125 ns->ns_idns = idns;
2139 2126 ns->ns_id = nsid;
2140 2127 ns->ns_block_count = idns->id_nsize;
2141 2128 ns->ns_block_size =
2142 2129 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2143 2130 ns->ns_best_block_size = ns->ns_block_size;
2144 2131
2145 2132 /*
2146 2133 * Get the EUI64 if present. Use it for devid and device node names.
2147 2134 */
2148 2135 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2149 2136 bcopy(idns->id_eui64, ns->ns_eui64, sizeof (ns->ns_eui64));
2150 2137
2151 2138 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
2152 2139 if (*(uint64_t *)ns->ns_eui64 != 0) {
2153 2140 uint8_t *eui64 = ns->ns_eui64;
2154 2141
2155 2142 (void) snprintf(ns->ns_name, sizeof (ns->ns_name),
2156 2143 "%02x%02x%02x%02x%02x%02x%02x%02x",
2157 2144 eui64[0], eui64[1], eui64[2], eui64[3],
2158 2145 eui64[4], eui64[5], eui64[6], eui64[7]);
2159 2146 } else {
2160 2147 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), "%d",
2161 2148 ns->ns_id);
2162 2149
2163 2150 nvme_prepare_devid(nvme, ns->ns_id);
2164 2151 }
2165 2152
2166 2153 /*
2167 2154 * Find the LBA format with no metadata and the best relative
2168 2155 * performance. A value of 3 means "degraded", 0 is best.
2169 2156 */
2170 2157 last_rp = 3;
2171 2158 for (int j = 0; j <= idns->id_nlbaf; j++) {
2172 2159 if (idns->id_lbaf[j].lbaf_lbads == 0)
2173 2160 break;
2174 2161 if (idns->id_lbaf[j].lbaf_ms != 0)
2175 2162 continue;
2176 2163 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2177 2164 continue;
2178 2165 last_rp = idns->id_lbaf[j].lbaf_rp;
2179 2166 ns->ns_best_block_size =
2180 2167 1 << idns->id_lbaf[j].lbaf_lbads;
2181 2168 }
2182 2169
2183 2170 if (ns->ns_best_block_size < nvme->n_min_block_size)
2184 2171 ns->ns_best_block_size = nvme->n_min_block_size;
2185 2172
2186 2173 /*
2187 2174 * We currently don't support namespaces that use either:
2188 2175 * - thin provisioning
2189 2176 * - protection information
2190 2177 * - illegal block size (< 512)
2191 2178 */
2192 2179 if (idns->id_nsfeat.f_thin ||
2193 2180 idns->id_dps.dp_pinfo) {
2194 2181 dev_err(nvme->n_dip, CE_WARN,
2195 2182 "!ignoring namespace %d, unsupported features: "
2196 2183 "thin = %d, pinfo = %d", nsid,
2197 2184 idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo);
2198 2185 ns->ns_ignore = B_TRUE;
2199 2186 } else if (ns->ns_block_size < 512) {
2200 2187 dev_err(nvme->n_dip, CE_WARN,
2201 2188 "!ignoring namespace %d, unsupported block size %"PRIu64,
2202 2189 nsid, (uint64_t)ns->ns_block_size);
2203 2190 ns->ns_ignore = B_TRUE;
2204 2191 } else {
2205 2192 ns->ns_ignore = B_FALSE;
2206 2193 }
2207 2194
2208 2195 return (DDI_SUCCESS);
2209 2196 }
2210 2197
2211 2198 static int
2212 2199 nvme_init(nvme_t *nvme)
2213 2200 {
2214 2201 nvme_reg_cc_t cc = { 0 };
2215 2202 nvme_reg_aqa_t aqa = { 0 };
2216 2203 nvme_reg_asq_t asq = { 0 };
2217 2204 nvme_reg_acq_t acq = { 0 };
2218 2205 nvme_reg_cap_t cap;
2219 2206 nvme_reg_vs_t vs;
2220 2207 nvme_reg_csts_t csts;
2221 2208 int i = 0;
2222 2209 int nqueues;
2223 2210 char model[sizeof (nvme->n_idctl->id_model) + 1];
2224 2211 char *vendor, *product;
2225 2212
2226 2213 /* Check controller version */
2227 2214 vs.r = nvme_get32(nvme, NVME_REG_VS);
2228 2215 nvme->n_version.v_major = vs.b.vs_mjr;
2229 2216 nvme->n_version.v_minor = vs.b.vs_mnr;
2230 2217 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
2231 2218 nvme->n_version.v_major, nvme->n_version.v_minor);
2232 2219
2233 2220 if (NVME_VERSION_HIGHER(&nvme->n_version,
2234 2221 nvme_version_major, nvme_version_minor)) {
2235 2222 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d",
2236 2223 nvme_version_major, nvme_version_minor);
2237 2224 if (nvme->n_strict_version)
2238 2225 goto fail;
2239 2226 }
2240 2227
2241 2228 /* retrieve controller configuration */
2242 2229 cap.r = nvme_get64(nvme, NVME_REG_CAP);
2243 2230
2244 2231 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
2245 2232 dev_err(nvme->n_dip, CE_WARN,
2246 2233 "!NVM command set not supported by hardware");
2247 2234 goto fail;
2248 2235 }
2249 2236
2250 2237 nvme->n_nssr_supported = cap.b.cap_nssrs;
2251 2238 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
2252 2239 nvme->n_timeout = cap.b.cap_to;
2253 2240 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
2254 2241 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
2255 2242 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
2256 2243
2257 2244 /*
2258 2245 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
2259 2246 * the base page size of 4k (1<<12), so add 12 here to get the real
2260 2247 * page size value.
2261 2248 */
2262 2249 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
2263 2250 cap.b.cap_mpsmax + 12);
2264 2251 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
2265 2252
2266 2253 /*
2267 2254 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
2268 2255 */
2269 2256 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
2270 2257 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2271 2258
2272 2259 /*
2273 2260 * Set up PRP DMA to transfer 1 page-aligned page at a time.
2274 2261 * Maxxfer may be increased after we identified the controller limits.
2275 2262 */
2276 2263 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
2277 2264 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
2278 2265 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
2279 2266 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
2280 2267
2281 2268 /*
2282 2269 * Reset controller if it's still in ready state.
2283 2270 */
2284 2271 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
2285 2272 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
2286 2273 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2287 2274 nvme->n_dead = B_TRUE;
2288 2275 goto fail;
2289 2276 }
2290 2277
2291 2278 /*
2292 2279 * Create the admin queue pair.
2293 2280 */
2294 2281 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
2295 2282 != DDI_SUCCESS) {
2296 2283 dev_err(nvme->n_dip, CE_WARN,
2297 2284 "!unable to allocate admin qpair");
2298 2285 goto fail;
2299 2286 }
2300 2287 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
2301 2288 nvme->n_ioq[0] = nvme->n_adminq;
2302 2289
2303 2290 nvme->n_progress |= NVME_ADMIN_QUEUE;
2304 2291
2305 2292 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2306 2293 "admin-queue-len", nvme->n_admin_queue_len);
2307 2294
2308 2295 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
2309 2296 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
2310 2297 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
2311 2298
2312 2299 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
2313 2300 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
2314 2301
2315 2302 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
2316 2303 nvme_put64(nvme, NVME_REG_ASQ, asq);
2317 2304 nvme_put64(nvme, NVME_REG_ACQ, acq);
2318 2305
2319 2306 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
2320 2307 cc.b.cc_css = 0; /* use NVM command set */
2321 2308 cc.b.cc_mps = nvme->n_pageshift - 12;
2322 2309 cc.b.cc_shn = 0; /* no shutdown in progress */
2323 2310 cc.b.cc_en = 1; /* enable controller */
2324 2311 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
2325 2312 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
2326 2313
2327 2314 nvme_put32(nvme, NVME_REG_CC, cc.r);
2328 2315
2329 2316 /*
2330 2317 * Wait for the controller to become ready.
2331 2318 */
2332 2319 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2333 2320 if (csts.b.csts_rdy == 0) {
2334 2321 for (i = 0; i != nvme->n_timeout * 10; i++) {
2335 2322 delay(drv_usectohz(50000));
2336 2323 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
2337 2324
2338 2325 if (csts.b.csts_cfs == 1) {
2339 2326 dev_err(nvme->n_dip, CE_WARN,
2340 2327 "!controller fatal status at init");
2341 2328 ddi_fm_service_impact(nvme->n_dip,
2342 2329 DDI_SERVICE_LOST);
2343 2330 nvme->n_dead = B_TRUE;
2344 2331 goto fail;
2345 2332 }
2346 2333
2347 2334 if (csts.b.csts_rdy == 1)
2348 2335 break;
2349 2336 }
2350 2337 }
2351 2338
2352 2339 if (csts.b.csts_rdy == 0) {
2353 2340 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
2354 2341 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2355 2342 nvme->n_dead = B_TRUE;
2356 2343 goto fail;
2357 2344 }
2358 2345
2359 2346 /*
2360 2347 * Assume an abort command limit of 1. We'll destroy and re-init
2361 2348 * that later when we know the true abort command limit.
2362 2349 */
2363 2350 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
2364 2351
2365 2352 /*
2366 2353 * Setup initial interrupt for admin queue.
2367 2354 */
2368 2355 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
2369 2356 != DDI_SUCCESS) &&
2370 2357 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
2371 2358 != DDI_SUCCESS) &&
↓ open down ↓ |
796 lines elided |
↑ open up ↑ |
2372 2359 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
2373 2360 != DDI_SUCCESS)) {
2374 2361 dev_err(nvme->n_dip, CE_WARN,
2375 2362 "!failed to setup initial interrupt");
2376 2363 goto fail;
2377 2364 }
2378 2365
2379 2366 /*
2380 2367 * Post an asynchronous event command to catch errors.
2381 2368 */
2382 - if (nvme_async_event(nvme) != DDI_SUCCESS) {
2383 - dev_err(nvme->n_dip, CE_WARN,
2384 - "!failed to post async event");
2385 - goto fail;
2386 - }
2369 + nvme_async_event(nvme);
2387 2370
2388 2371 /*
2389 2372 * Identify Controller
2390 2373 */
2391 2374 nvme->n_idctl = nvme_identify(nvme, 0);
2392 2375 if (nvme->n_idctl == NULL) {
2393 2376 dev_err(nvme->n_dip, CE_WARN,
2394 2377 "!failed to identify controller");
2395 2378 goto fail;
2396 2379 }
2397 2380
2398 2381 /*
2399 2382 * Get Vendor & Product ID
2400 2383 */
2401 2384 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2402 2385 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2403 2386 sata_split_model(model, &vendor, &product);
2404 2387
2405 2388 if (vendor == NULL)
2406 2389 nvme->n_vendor = strdup("NVMe");
2407 2390 else
2408 2391 nvme->n_vendor = strdup(vendor);
2409 2392
2410 2393 nvme->n_product = strdup(product);
2411 2394
2412 2395 /*
2413 2396 * Get controller limits.
2414 2397 */
2415 2398 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
2416 2399 MIN(nvme->n_admin_queue_len / 10,
2417 2400 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
2418 2401
2419 2402 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2420 2403 "async-event-limit", nvme->n_async_event_limit);
2421 2404
2422 2405 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
2423 2406
2424 2407 /*
2425 2408 * Reinitialize the semaphore with the true abort command limit
2426 2409 * supported by the hardware. It's not necessary to disable interrupts
2427 2410 * as only command aborts use the semaphore, and no commands are
2428 2411 * executed or aborted while we're here.
2429 2412 */
2430 2413 sema_destroy(&nvme->n_abort_sema);
2431 2414 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
2432 2415 SEMA_DRIVER, NULL);
2433 2416
2434 2417 nvme->n_progress |= NVME_CTRL_LIMITS;
2435 2418
2436 2419 if (nvme->n_idctl->id_mdts == 0)
2437 2420 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
2438 2421 else
2439 2422 nvme->n_max_data_transfer_size =
2440 2423 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
2441 2424
2442 2425 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
2443 2426
2444 2427 /*
2445 2428 * Limit n_max_data_transfer_size to what we can handle in one PRP.
2446 2429 * Chained PRPs are currently unsupported.
2447 2430 *
2448 2431 * This is a no-op on hardware which doesn't support a transfer size
2449 2432 * big enough to require chained PRPs.
2450 2433 */
2451 2434 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
2452 2435 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
2453 2436
2454 2437 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
2455 2438
2456 2439 /*
2457 2440 * Make sure the minimum/maximum queue entry sizes are not
2458 2441 * larger/smaller than the default.
2459 2442 */
2460 2443
2461 2444 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
2462 2445 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
2463 2446 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
2464 2447 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
2465 2448 goto fail;
2466 2449
2467 2450 /*
2468 2451 * Check for the presence of a Volatile Write Cache. If present,
2469 2452 * enable or disable based on the value of the property
2470 2453 * volatile-write-cache-enable (default is enabled).
2471 2454 */
2472 2455 nvme->n_write_cache_present =
2473 2456 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE;
2474 2457
2475 2458 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2476 2459 "volatile-write-cache-present",
2477 2460 nvme->n_write_cache_present ? 1 : 0);
2478 2461
2479 2462 if (!nvme->n_write_cache_present) {
2480 2463 nvme->n_write_cache_enabled = B_FALSE;
2481 2464 } else if (!nvme_write_cache_set(nvme, nvme->n_write_cache_enabled)) {
2482 2465 dev_err(nvme->n_dip, CE_WARN,
2483 2466 "!failed to %sable volatile write cache",
2484 2467 nvme->n_write_cache_enabled ? "en" : "dis");
2485 2468 /*
2486 2469 * Assume the cache is (still) enabled.
2487 2470 */
2488 2471 nvme->n_write_cache_enabled = B_TRUE;
2489 2472 }
2490 2473
2491 2474 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2492 2475 "volatile-write-cache-enable",
2493 2476 nvme->n_write_cache_enabled ? 1 : 0);
2494 2477
2495 2478 /*
2496 2479 * Assume LBA Range Type feature is supported. If it isn't this
2497 2480 * will be set to B_FALSE by nvme_get_features().
2498 2481 */
2499 2482 nvme->n_lba_range_supported = B_TRUE;
2500 2483
2501 2484 /*
2502 2485 * Check support for Autonomous Power State Transition.
2503 2486 */
2504 2487 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2505 2488 nvme->n_auto_pst_supported =
2506 2489 nvme->n_idctl->id_apsta.ap_sup == 0 ? B_FALSE : B_TRUE;
2507 2490
2508 2491 /*
2509 2492 * Identify Namespaces
2510 2493 */
2511 2494 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2512 2495 if (nvme->n_namespace_count > NVME_MINOR_MAX) {
2513 2496 dev_err(nvme->n_dip, CE_WARN,
2514 2497 "!too many namespaces: %d, limiting to %d\n",
2515 2498 nvme->n_namespace_count, NVME_MINOR_MAX);
2516 2499 nvme->n_namespace_count = NVME_MINOR_MAX;
2517 2500 }
2518 2501
2519 2502 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2520 2503 nvme->n_namespace_count, KM_SLEEP);
2521 2504
2522 2505 for (i = 0; i != nvme->n_namespace_count; i++) {
2523 2506 mutex_init(&nvme->n_ns[i].ns_minor.nm_mutex, NULL, MUTEX_DRIVER,
2524 2507 NULL);
2525 2508 if (nvme_init_ns(nvme, i + 1) != DDI_SUCCESS)
2526 2509 goto fail;
2527 2510 }
2528 2511
2529 2512 /*
2530 2513 * Try to set up MSI/MSI-X interrupts.
2531 2514 */
2532 2515 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2533 2516 != 0) {
2534 2517 nvme_release_interrupts(nvme);
2535 2518
2536 2519 nqueues = MIN(UINT16_MAX, ncpus);
2537 2520
2538 2521 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2539 2522 nqueues) != DDI_SUCCESS) &&
2540 2523 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2541 2524 nqueues) != DDI_SUCCESS)) {
2542 2525 dev_err(nvme->n_dip, CE_WARN,
2543 2526 "!failed to setup MSI/MSI-X interrupts");
2544 2527 goto fail;
2545 2528 }
2546 2529 }
2547 2530
2548 2531 nqueues = nvme->n_intr_cnt;
2549 2532
2550 2533 /*
2551 2534 * Create I/O queue pairs.
2552 2535 */
2553 2536 nvme->n_ioq_count = nvme_set_nqueues(nvme, nqueues);
2554 2537 if (nvme->n_ioq_count == 0) {
2555 2538 dev_err(nvme->n_dip, CE_WARN,
2556 2539 "!failed to set number of I/O queues to %d", nqueues);
2557 2540 goto fail;
2558 2541 }
2559 2542
2560 2543 /*
2561 2544 * Reallocate I/O queue array
2562 2545 */
2563 2546 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2564 2547 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2565 2548 (nvme->n_ioq_count + 1), KM_SLEEP);
2566 2549 nvme->n_ioq[0] = nvme->n_adminq;
2567 2550
2568 2551 /*
2569 2552 * If we got less queues than we asked for we might as well give
2570 2553 * some of the interrupt vectors back to the system.
2571 2554 */
2572 2555 if (nvme->n_ioq_count < nqueues) {
2573 2556 nvme_release_interrupts(nvme);
2574 2557
2575 2558 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2576 2559 nvme->n_ioq_count) != DDI_SUCCESS) {
2577 2560 dev_err(nvme->n_dip, CE_WARN,
2578 2561 "!failed to reduce number of interrupts");
2579 2562 goto fail;
2580 2563 }
2581 2564 }
2582 2565
2583 2566 /*
2584 2567 * Alloc & register I/O queue pairs
2585 2568 */
2586 2569 nvme->n_io_queue_len =
2587 2570 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2588 2571 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2589 2572 nvme->n_io_queue_len);
2590 2573
2591 2574 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2592 2575 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2593 2576 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2594 2577 dev_err(nvme->n_dip, CE_WARN,
2595 2578 "!unable to allocate I/O qpair %d", i);
2596 2579 goto fail;
2597 2580 }
2598 2581
2599 2582 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i)
2600 2583 != DDI_SUCCESS) {
↓ open down ↓ |
204 lines elided |
↑ open up ↑ |
2601 2584 dev_err(nvme->n_dip, CE_WARN,
2602 2585 "!unable to create I/O qpair %d", i);
2603 2586 goto fail;
2604 2587 }
2605 2588 }
2606 2589
2607 2590 /*
2608 2591 * Post more asynchronous events commands to reduce event reporting
2609 2592 * latency as suggested by the spec.
2610 2593 */
2611 - for (i = 1; i != nvme->n_async_event_limit; i++) {
2612 - if (nvme_async_event(nvme) != DDI_SUCCESS) {
2613 - dev_err(nvme->n_dip, CE_WARN,
2614 - "!failed to post async event %d", i);
2615 - goto fail;
2616 - }
2617 - }
2594 + for (i = 1; i != nvme->n_async_event_limit; i++)
2595 + nvme_async_event(nvme);
2618 2596
2619 2597 return (DDI_SUCCESS);
2620 2598
2621 2599 fail:
2622 2600 (void) nvme_reset(nvme, B_FALSE);
2623 2601 return (DDI_FAILURE);
2624 2602 }
2625 2603
2626 2604 static uint_t
2627 2605 nvme_intr(caddr_t arg1, caddr_t arg2)
2628 2606 {
2629 2607 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2630 2608 nvme_t *nvme = (nvme_t *)arg1;
2631 2609 int inum = (int)(uintptr_t)arg2;
2632 2610 int ccnt = 0;
2633 2611 int qnum;
2634 2612 nvme_cmd_t *cmd;
2635 2613
2636 2614 if (inum >= nvme->n_intr_cnt)
2637 2615 return (DDI_INTR_UNCLAIMED);
2638 2616
2639 2617 /*
2640 2618 * The interrupt vector a queue uses is calculated as queue_idx %
2641 2619 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2642 2620 * in steps of n_intr_cnt to process all queues using this vector.
2643 2621 */
2644 2622 for (qnum = inum;
2645 2623 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2646 2624 qnum += nvme->n_intr_cnt) {
2647 2625 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) {
2648 2626 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
2649 2627 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
2650 2628 ccnt++;
2651 2629 }
2652 2630 }
2653 2631
2654 2632 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2655 2633 }
2656 2634
2657 2635 static void
2658 2636 nvme_release_interrupts(nvme_t *nvme)
2659 2637 {
2660 2638 int i;
2661 2639
2662 2640 for (i = 0; i < nvme->n_intr_cnt; i++) {
2663 2641 if (nvme->n_inth[i] == NULL)
2664 2642 break;
2665 2643
2666 2644 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2667 2645 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2668 2646 else
2669 2647 (void) ddi_intr_disable(nvme->n_inth[i]);
2670 2648
2671 2649 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2672 2650 (void) ddi_intr_free(nvme->n_inth[i]);
2673 2651 }
2674 2652
2675 2653 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2676 2654 nvme->n_inth = NULL;
2677 2655 nvme->n_inth_sz = 0;
2678 2656
2679 2657 nvme->n_progress &= ~NVME_INTERRUPTS;
2680 2658 }
2681 2659
2682 2660 static int
2683 2661 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2684 2662 {
2685 2663 int nintrs, navail, count;
2686 2664 int ret;
2687 2665 int i;
2688 2666
2689 2667 if (nvme->n_intr_types == 0) {
2690 2668 ret = ddi_intr_get_supported_types(nvme->n_dip,
2691 2669 &nvme->n_intr_types);
2692 2670 if (ret != DDI_SUCCESS) {
2693 2671 dev_err(nvme->n_dip, CE_WARN,
2694 2672 "!%s: ddi_intr_get_supported types failed",
2695 2673 __func__);
2696 2674 return (ret);
2697 2675 }
2698 2676 #ifdef __x86
2699 2677 if (get_hwenv() == HW_VMWARE)
2700 2678 nvme->n_intr_types &= ~DDI_INTR_TYPE_MSIX;
2701 2679 #endif
2702 2680 }
2703 2681
2704 2682 if ((nvme->n_intr_types & intr_type) == 0)
2705 2683 return (DDI_FAILURE);
2706 2684
2707 2685 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2708 2686 if (ret != DDI_SUCCESS) {
2709 2687 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2710 2688 __func__);
2711 2689 return (ret);
2712 2690 }
2713 2691
2714 2692 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2715 2693 if (ret != DDI_SUCCESS) {
2716 2694 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2717 2695 __func__);
2718 2696 return (ret);
2719 2697 }
2720 2698
2721 2699 /* We want at most one interrupt per queue pair. */
2722 2700 if (navail > nqpairs)
2723 2701 navail = nqpairs;
2724 2702
2725 2703 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2726 2704 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2727 2705
2728 2706 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2729 2707 &count, 0);
2730 2708 if (ret != DDI_SUCCESS) {
2731 2709 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2732 2710 __func__);
2733 2711 goto fail;
2734 2712 }
2735 2713
2736 2714 nvme->n_intr_cnt = count;
2737 2715
2738 2716 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2739 2717 if (ret != DDI_SUCCESS) {
2740 2718 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2741 2719 __func__);
2742 2720 goto fail;
2743 2721 }
2744 2722
2745 2723 for (i = 0; i < count; i++) {
2746 2724 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2747 2725 (void *)nvme, (void *)(uintptr_t)i);
2748 2726 if (ret != DDI_SUCCESS) {
2749 2727 dev_err(nvme->n_dip, CE_WARN,
2750 2728 "!%s: ddi_intr_add_handler failed", __func__);
2751 2729 goto fail;
2752 2730 }
2753 2731 }
2754 2732
2755 2733 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2756 2734
2757 2735 for (i = 0; i < count; i++) {
2758 2736 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2759 2737 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2760 2738 else
2761 2739 ret = ddi_intr_enable(nvme->n_inth[i]);
2762 2740
2763 2741 if (ret != DDI_SUCCESS) {
2764 2742 dev_err(nvme->n_dip, CE_WARN,
2765 2743 "!%s: enabling interrupt %d failed", __func__, i);
2766 2744 goto fail;
2767 2745 }
2768 2746 }
2769 2747
2770 2748 nvme->n_intr_type = intr_type;
2771 2749
2772 2750 nvme->n_progress |= NVME_INTERRUPTS;
2773 2751
2774 2752 return (DDI_SUCCESS);
2775 2753
2776 2754 fail:
2777 2755 nvme_release_interrupts(nvme);
2778 2756
2779 2757 return (ret);
2780 2758 }
2781 2759
2782 2760 static int
2783 2761 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2784 2762 {
2785 2763 _NOTE(ARGUNUSED(arg));
2786 2764
2787 2765 pci_ereport_post(dip, fm_error, NULL);
2788 2766 return (fm_error->fme_status);
2789 2767 }
2790 2768
2791 2769 static int
2792 2770 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2793 2771 {
2794 2772 nvme_t *nvme;
2795 2773 int instance;
2796 2774 int nregs;
2797 2775 off_t regsize;
2798 2776 int i;
2799 2777 char name[32];
2800 2778
2801 2779 if (cmd != DDI_ATTACH)
2802 2780 return (DDI_FAILURE);
2803 2781
2804 2782 instance = ddi_get_instance(dip);
2805 2783
2806 2784 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2807 2785 return (DDI_FAILURE);
2808 2786
2809 2787 nvme = ddi_get_soft_state(nvme_state, instance);
2810 2788 ddi_set_driver_private(dip, nvme);
2811 2789 nvme->n_dip = dip;
2812 2790
2813 2791 mutex_init(&nvme->n_minor.nm_mutex, NULL, MUTEX_DRIVER, NULL);
2814 2792
2815 2793 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2816 2794 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2817 2795 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2818 2796 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2819 2797 B_TRUE : B_FALSE;
2820 2798 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2821 2799 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2822 2800 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2823 2801 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2824 2802 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2825 2803 DDI_PROP_DONTPASS, "async-event-limit",
2826 2804 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2827 2805 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2828 2806 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ?
2829 2807 B_TRUE : B_FALSE;
2830 2808 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2831 2809 DDI_PROP_DONTPASS, "min-phys-block-size",
2832 2810 NVME_DEFAULT_MIN_BLOCK_SIZE);
2833 2811
2834 2812 if (!ISP2(nvme->n_min_block_size) ||
2835 2813 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) {
2836 2814 dev_err(dip, CE_WARN, "!min-phys-block-size %s, "
2837 2815 "using default %d", ISP2(nvme->n_min_block_size) ?
2838 2816 "too low" : "not a power of 2",
2839 2817 NVME_DEFAULT_MIN_BLOCK_SIZE);
2840 2818 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE;
2841 2819 }
2842 2820
2843 2821 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2844 2822 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2845 2823 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2846 2824 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2847 2825
2848 2826 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2849 2827 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2850 2828
2851 2829 if (nvme->n_async_event_limit < 1)
2852 2830 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2853 2831
2854 2832 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2855 2833 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2856 2834 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2857 2835 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2858 2836
2859 2837 /*
2860 2838 * Setup FMA support.
2861 2839 */
2862 2840 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2863 2841 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2864 2842 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2865 2843 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2866 2844
2867 2845 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2868 2846
2869 2847 if (nvme->n_fm_cap) {
2870 2848 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2871 2849 nvme->n_reg_acc_attr.devacc_attr_access =
2872 2850 DDI_FLAGERR_ACC;
2873 2851
2874 2852 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2875 2853 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2876 2854 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2877 2855 }
2878 2856
2879 2857 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2880 2858 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2881 2859 pci_ereport_setup(dip);
2882 2860
2883 2861 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2884 2862 ddi_fm_handler_register(dip, nvme_fm_errcb,
2885 2863 (void *)nvme);
2886 2864 }
2887 2865
2888 2866 nvme->n_progress |= NVME_FMA_INIT;
2889 2867
2890 2868 /*
2891 2869 * The spec defines several register sets. Only the controller
2892 2870 * registers (set 1) are currently used.
2893 2871 */
2894 2872 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2895 2873 nregs < 2 ||
2896 2874 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2897 2875 goto fail;
2898 2876
2899 2877 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2900 2878 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2901 2879 dev_err(dip, CE_WARN, "!failed to map regset 1");
2902 2880 goto fail;
2903 2881 }
2904 2882
2905 2883 nvme->n_progress |= NVME_REGS_MAPPED;
2906 2884
2907 2885 /*
2908 2886 * Create taskq for command completion.
2909 2887 */
2910 2888 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2911 2889 ddi_driver_name(dip), ddi_get_instance(dip));
2912 2890 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2913 2891 TASKQ_DEFAULTPRI, 0);
2914 2892 if (nvme->n_cmd_taskq == NULL) {
2915 2893 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2916 2894 goto fail;
2917 2895 }
2918 2896
2919 2897 /*
2920 2898 * Create PRP DMA cache
2921 2899 */
2922 2900 (void) snprintf(name, sizeof (name), "%s%d_prp_cache",
2923 2901 ddi_driver_name(dip), ddi_get_instance(dip));
2924 2902 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t),
2925 2903 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor,
2926 2904 NULL, (void *)nvme, NULL, 0);
2927 2905
2928 2906 if (nvme_init(nvme) != DDI_SUCCESS)
2929 2907 goto fail;
2930 2908
2931 2909 /*
2932 2910 * Attach the blkdev driver for each namespace.
2933 2911 */
2934 2912 for (i = 0; i != nvme->n_namespace_count; i++) {
2935 2913 if (ddi_create_minor_node(nvme->n_dip, nvme->n_ns[i].ns_name,
2936 2914 S_IFCHR, NVME_MINOR(ddi_get_instance(nvme->n_dip), i + 1),
2937 2915 DDI_NT_NVME_ATTACHMENT_POINT, 0) != DDI_SUCCESS) {
2938 2916 dev_err(dip, CE_WARN,
2939 2917 "!failed to create minor node for namespace %d", i);
2940 2918 goto fail;
2941 2919 }
2942 2920
2943 2921 if (nvme->n_ns[i].ns_ignore)
2944 2922 continue;
2945 2923
2946 2924 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
2947 2925 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2948 2926
2949 2927 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
2950 2928 dev_err(dip, CE_WARN,
2951 2929 "!failed to get blkdev handle for namespace %d", i);
2952 2930 goto fail;
2953 2931 }
2954 2932
2955 2933 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
2956 2934 != DDI_SUCCESS) {
2957 2935 dev_err(dip, CE_WARN,
2958 2936 "!failed to attach blkdev handle for namespace %d",
2959 2937 i);
2960 2938 goto fail;
2961 2939 }
2962 2940 }
2963 2941
2964 2942 if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
2965 2943 NVME_MINOR(ddi_get_instance(dip), 0), DDI_NT_NVME_NEXUS, 0)
2966 2944 != DDI_SUCCESS) {
2967 2945 dev_err(dip, CE_WARN, "nvme_attach: "
2968 2946 "cannot create devctl minor node");
2969 2947 goto fail;
2970 2948 }
2971 2949
2972 2950 return (DDI_SUCCESS);
2973 2951
2974 2952 fail:
2975 2953 /* attach successful anyway so that FMA can retire the device */
2976 2954 if (nvme->n_dead)
2977 2955 return (DDI_SUCCESS);
2978 2956
2979 2957 (void) nvme_detach(dip, DDI_DETACH);
2980 2958
2981 2959 return (DDI_FAILURE);
2982 2960 }
2983 2961
2984 2962 static int
2985 2963 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2986 2964 {
2987 2965 int instance, i;
2988 2966 nvme_t *nvme;
2989 2967
2990 2968 if (cmd != DDI_DETACH)
2991 2969 return (DDI_FAILURE);
2992 2970
2993 2971 instance = ddi_get_instance(dip);
2994 2972
2995 2973 nvme = ddi_get_soft_state(nvme_state, instance);
2996 2974
2997 2975 if (nvme == NULL)
2998 2976 return (DDI_FAILURE);
2999 2977
3000 2978 ddi_remove_minor_node(dip, "devctl");
3001 2979 mutex_destroy(&nvme->n_minor.nm_mutex);
3002 2980
3003 2981 if (nvme->n_ns) {
3004 2982 for (i = 0; i != nvme->n_namespace_count; i++) {
3005 2983 ddi_remove_minor_node(dip, nvme->n_ns[i].ns_name);
3006 2984 mutex_destroy(&nvme->n_ns[i].ns_minor.nm_mutex);
3007 2985
3008 2986 if (nvme->n_ns[i].ns_bd_hdl) {
3009 2987 (void) bd_detach_handle(
3010 2988 nvme->n_ns[i].ns_bd_hdl);
3011 2989 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
3012 2990 }
3013 2991
3014 2992 if (nvme->n_ns[i].ns_idns)
3015 2993 kmem_free(nvme->n_ns[i].ns_idns,
3016 2994 sizeof (nvme_identify_nsid_t));
3017 2995 if (nvme->n_ns[i].ns_devid)
3018 2996 strfree(nvme->n_ns[i].ns_devid);
3019 2997 }
3020 2998
3021 2999 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
3022 3000 nvme->n_namespace_count);
3023 3001 }
3024 3002
3025 3003 if (nvme->n_progress & NVME_INTERRUPTS)
3026 3004 nvme_release_interrupts(nvme);
3027 3005
3028 3006 if (nvme->n_cmd_taskq)
3029 3007 ddi_taskq_wait(nvme->n_cmd_taskq);
3030 3008
3031 3009 if (nvme->n_ioq_count > 0) {
3032 3010 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
3033 3011 if (nvme->n_ioq[i] != NULL) {
3034 3012 /* TODO: send destroy queue commands */
3035 3013 nvme_free_qpair(nvme->n_ioq[i]);
3036 3014 }
3037 3015 }
3038 3016
3039 3017 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
3040 3018 (nvme->n_ioq_count + 1));
3041 3019 }
3042 3020
3043 3021 if (nvme->n_prp_cache != NULL) {
3044 3022 kmem_cache_destroy(nvme->n_prp_cache);
3045 3023 }
3046 3024
3047 3025 if (nvme->n_progress & NVME_REGS_MAPPED) {
3048 3026 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
3049 3027 (void) nvme_reset(nvme, B_FALSE);
3050 3028 }
3051 3029
3052 3030 if (nvme->n_cmd_taskq)
3053 3031 ddi_taskq_destroy(nvme->n_cmd_taskq);
3054 3032
3055 3033 if (nvme->n_progress & NVME_CTRL_LIMITS)
3056 3034 sema_destroy(&nvme->n_abort_sema);
3057 3035
3058 3036 if (nvme->n_progress & NVME_ADMIN_QUEUE)
3059 3037 nvme_free_qpair(nvme->n_adminq);
3060 3038
3061 3039 if (nvme->n_idctl)
3062 3040 kmem_free(nvme->n_idctl, NVME_IDENTIFY_BUFSIZE);
3063 3041
3064 3042 if (nvme->n_progress & NVME_REGS_MAPPED)
3065 3043 ddi_regs_map_free(&nvme->n_regh);
3066 3044
3067 3045 if (nvme->n_progress & NVME_FMA_INIT) {
3068 3046 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3069 3047 ddi_fm_handler_unregister(nvme->n_dip);
3070 3048
3071 3049 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
3072 3050 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
3073 3051 pci_ereport_teardown(nvme->n_dip);
3074 3052
3075 3053 ddi_fm_fini(nvme->n_dip);
3076 3054 }
3077 3055
3078 3056 if (nvme->n_vendor != NULL)
3079 3057 strfree(nvme->n_vendor);
3080 3058
3081 3059 if (nvme->n_product != NULL)
3082 3060 strfree(nvme->n_product);
3083 3061
3084 3062 ddi_soft_state_free(nvme_state, instance);
3085 3063
3086 3064 return (DDI_SUCCESS);
3087 3065 }
3088 3066
3089 3067 static int
3090 3068 nvme_quiesce(dev_info_t *dip)
3091 3069 {
3092 3070 int instance;
3093 3071 nvme_t *nvme;
3094 3072
3095 3073 instance = ddi_get_instance(dip);
3096 3074
3097 3075 nvme = ddi_get_soft_state(nvme_state, instance);
3098 3076
3099 3077 if (nvme == NULL)
3100 3078 return (DDI_FAILURE);
3101 3079
3102 3080 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
3103 3081
3104 3082 (void) nvme_reset(nvme, B_TRUE);
3105 3083
3106 3084 return (DDI_FAILURE);
3107 3085 }
3108 3086
3109 3087 static int
3110 3088 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
3111 3089 {
3112 3090 nvme_t *nvme = cmd->nc_nvme;
3113 3091 int nprp_page, nprp;
3114 3092 uint64_t *prp;
3115 3093
3116 3094 if (xfer->x_ndmac == 0)
3117 3095 return (DDI_FAILURE);
3118 3096
3119 3097 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
3120 3098 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3121 3099
3122 3100 if (xfer->x_ndmac == 1) {
3123 3101 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
3124 3102 return (DDI_SUCCESS);
3125 3103 } else if (xfer->x_ndmac == 2) {
3126 3104 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
3127 3105 return (DDI_SUCCESS);
3128 3106 }
3129 3107
3130 3108 xfer->x_ndmac--;
3131 3109
3132 3110 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
3133 3111 ASSERT(nprp_page > 0);
3134 3112 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
3135 3113
3136 3114 /*
3137 3115 * We currently don't support chained PRPs and set up our DMA
3138 3116 * attributes to reflect that. If we still get an I/O request
3139 3117 * that needs a chained PRP something is very wrong.
3140 3118 */
3141 3119 VERIFY(nprp == 1);
3142 3120
3143 3121 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP);
3144 3122 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len);
3145 3123
3146 3124 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
3147 3125
3148 3126 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
3149 3127 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
3150 3128 xfer->x_ndmac > 0;
3151 3129 prp++, xfer->x_ndmac--) {
3152 3130 *prp = xfer->x_dmac.dmac_laddress;
3153 3131 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
3154 3132 }
3155 3133
3156 3134 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
3157 3135 DDI_DMA_SYNC_FORDEV);
3158 3136 return (DDI_SUCCESS);
3159 3137 }
3160 3138
3161 3139 static nvme_cmd_t *
3162 3140 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
3163 3141 {
3164 3142 nvme_t *nvme = ns->ns_nvme;
3165 3143 nvme_cmd_t *cmd;
3166 3144
3167 3145 /*
3168 3146 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
3169 3147 */
3170 3148 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
3171 3149 KM_NOSLEEP : KM_SLEEP);
3172 3150
3173 3151 if (cmd == NULL)
3174 3152 return (NULL);
3175 3153
3176 3154 cmd->nc_sqe.sqe_opc = opc;
3177 3155 cmd->nc_callback = nvme_bd_xfer_done;
3178 3156 cmd->nc_xfer = xfer;
3179 3157
3180 3158 switch (opc) {
3181 3159 case NVME_OPC_NVM_WRITE:
3182 3160 case NVME_OPC_NVM_READ:
3183 3161 VERIFY(xfer->x_nblks <= 0x10000);
3184 3162
3185 3163 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3186 3164
3187 3165 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
3188 3166 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
3189 3167 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
3190 3168
3191 3169 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
3192 3170 goto fail;
3193 3171 break;
3194 3172
3195 3173 case NVME_OPC_NVM_FLUSH:
3196 3174 cmd->nc_sqe.sqe_nsid = ns->ns_id;
3197 3175 break;
3198 3176
3199 3177 default:
3200 3178 goto fail;
3201 3179 }
3202 3180
3203 3181 return (cmd);
3204 3182
3205 3183 fail:
3206 3184 nvme_free_cmd(cmd);
3207 3185 return (NULL);
3208 3186 }
3209 3187
3210 3188 static void
3211 3189 nvme_bd_xfer_done(void *arg)
3212 3190 {
3213 3191 nvme_cmd_t *cmd = arg;
3214 3192 bd_xfer_t *xfer = cmd->nc_xfer;
3215 3193 int error = 0;
3216 3194
3217 3195 error = nvme_check_cmd_status(cmd);
3218 3196 nvme_free_cmd(cmd);
3219 3197
3220 3198 bd_xfer_done(xfer, error);
3221 3199 }
3222 3200
3223 3201 static void
3224 3202 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
3225 3203 {
3226 3204 nvme_namespace_t *ns = arg;
3227 3205 nvme_t *nvme = ns->ns_nvme;
3228 3206
3229 3207 /*
3230 3208 * blkdev maintains one queue size per instance (namespace),
3231 3209 * but all namespace share the I/O queues.
3232 3210 * TODO: need to figure out a sane default, or use per-NS I/O queues,
3233 3211 * or change blkdev to handle EAGAIN
3234 3212 */
3235 3213 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
3236 3214 / nvme->n_namespace_count;
3237 3215
3238 3216 /*
3239 3217 * d_maxxfer is not set, which means the value is taken from the DMA
3240 3218 * attributes specified to bd_alloc_handle.
3241 3219 */
3242 3220
3243 3221 drive->d_removable = B_FALSE;
3244 3222 drive->d_hotpluggable = B_FALSE;
3245 3223
3246 3224 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64));
3247 3225 drive->d_target = ns->ns_id;
3248 3226 drive->d_lun = 0;
3249 3227
3250 3228 drive->d_model = nvme->n_idctl->id_model;
3251 3229 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
3252 3230 drive->d_vendor = nvme->n_vendor;
3253 3231 drive->d_vendor_len = strlen(nvme->n_vendor);
3254 3232 drive->d_product = nvme->n_product;
3255 3233 drive->d_product_len = strlen(nvme->n_product);
3256 3234 drive->d_serial = nvme->n_idctl->id_serial;
3257 3235 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
3258 3236 drive->d_revision = nvme->n_idctl->id_fwrev;
3259 3237 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
3260 3238 }
3261 3239
3262 3240 static int
3263 3241 nvme_bd_mediainfo(void *arg, bd_media_t *media)
3264 3242 {
3265 3243 nvme_namespace_t *ns = arg;
3266 3244
3267 3245 media->m_nblks = ns->ns_block_count;
3268 3246 media->m_blksize = ns->ns_block_size;
3269 3247 media->m_readonly = B_FALSE;
3270 3248 media->m_solidstate = B_TRUE;
↓ open down ↓ |
643 lines elided |
↑ open up ↑ |
3271 3249
3272 3250 media->m_pblksize = ns->ns_best_block_size;
3273 3251
3274 3252 return (0);
3275 3253 }
3276 3254
3277 3255 static int
3278 3256 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
3279 3257 {
3280 3258 nvme_t *nvme = ns->ns_nvme;
3281 - nvme_cmd_t *cmd, *ret;
3259 + nvme_cmd_t *cmd;
3282 3260 nvme_qpair_t *ioq;
3283 3261 boolean_t poll;
3262 + int ret;
3284 3263
3285 3264 if (nvme->n_dead)
3286 3265 return (EIO);
3287 3266
3288 3267 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
3289 3268 if (cmd == NULL)
3290 3269 return (ENOMEM);
3291 3270
3292 3271 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
3293 3272 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
3294 3273 ioq = nvme->n_ioq[cmd->nc_sqid];
3295 3274
3296 3275 /*
3297 3276 * Get the polling flag before submitting the command. The command may
3298 3277 * complete immediately after it was submitted, which means we must
3299 3278 * treat both cmd and xfer as if they have been freed already.
3300 3279 */
3301 3280 poll = (xfer->x_flags & BD_XFER_POLL) != 0;
3302 3281
3303 - if (nvme_submit_cmd(ioq, cmd) != DDI_SUCCESS)
3304 - return (EAGAIN);
3282 + ret = nvme_submit_io_cmd(ioq, cmd);
3305 3283
3284 + if (ret != 0)
3285 + return (ret);
3286 +
3306 3287 if (!poll)
3307 3288 return (0);
3308 3289
3309 3290 do {
3310 - ret = nvme_retrieve_cmd(nvme, ioq);
3311 - if (ret != NULL)
3312 - nvme_bd_xfer_done(ret);
3291 + cmd = nvme_retrieve_cmd(nvme, ioq);
3292 + if (cmd != NULL)
3293 + nvme_bd_xfer_done(cmd);
3313 3294 else
3314 3295 drv_usecwait(10);
3315 3296 } while (ioq->nq_active_cmds != 0);
3316 3297
3317 3298 return (0);
3318 3299 }
3319 3300
3320 3301 static int
3321 3302 nvme_bd_read(void *arg, bd_xfer_t *xfer)
3322 3303 {
3323 3304 nvme_namespace_t *ns = arg;
3324 3305
3325 3306 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
3326 3307 }
3327 3308
3328 3309 static int
3329 3310 nvme_bd_write(void *arg, bd_xfer_t *xfer)
3330 3311 {
3331 3312 nvme_namespace_t *ns = arg;
3332 3313
3333 3314 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
3334 3315 }
3335 3316
3336 3317 static int
3337 3318 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
3338 3319 {
3339 3320 nvme_namespace_t *ns = arg;
3340 3321
3341 3322 if (ns->ns_nvme->n_dead)
3342 3323 return (EIO);
3343 3324
3344 3325 /*
3345 3326 * If the volatile write cache is not present or not enabled the FLUSH
3346 3327 * command is a no-op, so we can take a shortcut here.
3347 3328 */
3348 3329 if (!ns->ns_nvme->n_write_cache_present) {
3349 3330 bd_xfer_done(xfer, ENOTSUP);
3350 3331 return (0);
3351 3332 }
3352 3333
3353 3334 if (!ns->ns_nvme->n_write_cache_enabled) {
3354 3335 bd_xfer_done(xfer, 0);
3355 3336 return (0);
3356 3337 }
3357 3338
3358 3339 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
3359 3340 }
3360 3341
3361 3342 static int
3362 3343 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
3363 3344 {
3364 3345 nvme_namespace_t *ns = arg;
3365 3346
3366 3347 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
3367 3348 if (*(uint64_t *)ns->ns_eui64 != 0) {
3368 3349 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN,
3369 3350 sizeof (ns->ns_eui64), ns->ns_eui64, devid));
3370 3351 } else {
3371 3352 return (ddi_devid_init(devinfo, DEVID_ENCAP,
3372 3353 strlen(ns->ns_devid), ns->ns_devid, devid));
3373 3354 }
3374 3355 }
3375 3356
3376 3357 static int
3377 3358 nvme_open(dev_t *devp, int flag, int otyp, cred_t *cred_p)
3378 3359 {
3379 3360 #ifndef __lock_lint
3380 3361 _NOTE(ARGUNUSED(cred_p));
3381 3362 #endif
3382 3363 minor_t minor = getminor(*devp);
3383 3364 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3384 3365 int nsid = NVME_MINOR_NSID(minor);
3385 3366 nvme_minor_state_t *nm;
3386 3367 int rv = 0;
3387 3368
3388 3369 if (otyp != OTYP_CHR)
3389 3370 return (EINVAL);
3390 3371
3391 3372 if (nvme == NULL)
3392 3373 return (ENXIO);
3393 3374
3394 3375 if (nsid > nvme->n_namespace_count)
3395 3376 return (ENXIO);
3396 3377
3397 3378 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3398 3379
3399 3380 mutex_enter(&nm->nm_mutex);
3400 3381 if (nm->nm_oexcl) {
3401 3382 rv = EBUSY;
3402 3383 goto out;
3403 3384 }
3404 3385
3405 3386 if (flag & FEXCL) {
3406 3387 if (nm->nm_ocnt != 0) {
3407 3388 rv = EBUSY;
3408 3389 goto out;
3409 3390 }
3410 3391 nm->nm_oexcl = B_TRUE;
3411 3392 }
3412 3393
3413 3394 nm->nm_ocnt++;
3414 3395
3415 3396 out:
3416 3397 mutex_exit(&nm->nm_mutex);
3417 3398 return (rv);
3418 3399
3419 3400 }
3420 3401
3421 3402 static int
3422 3403 nvme_close(dev_t dev, int flag, int otyp, cred_t *cred_p)
3423 3404 {
3424 3405 #ifndef __lock_lint
3425 3406 _NOTE(ARGUNUSED(cred_p));
3426 3407 _NOTE(ARGUNUSED(flag));
3427 3408 #endif
3428 3409 minor_t minor = getminor(dev);
3429 3410 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3430 3411 int nsid = NVME_MINOR_NSID(minor);
3431 3412 nvme_minor_state_t *nm;
3432 3413
3433 3414 if (otyp != OTYP_CHR)
3434 3415 return (ENXIO);
3435 3416
3436 3417 if (nvme == NULL)
3437 3418 return (ENXIO);
3438 3419
3439 3420 if (nsid > nvme->n_namespace_count)
3440 3421 return (ENXIO);
3441 3422
3442 3423 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor;
3443 3424
3444 3425 mutex_enter(&nm->nm_mutex);
3445 3426 if (nm->nm_oexcl)
3446 3427 nm->nm_oexcl = B_FALSE;
3447 3428
3448 3429 ASSERT(nm->nm_ocnt > 0);
3449 3430 nm->nm_ocnt--;
3450 3431 mutex_exit(&nm->nm_mutex);
3451 3432
3452 3433 return (0);
3453 3434 }
3454 3435
3455 3436 static int
3456 3437 nvme_ioctl_identify(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3457 3438 cred_t *cred_p)
3458 3439 {
3459 3440 _NOTE(ARGUNUSED(cred_p));
3460 3441 int rv = 0;
3461 3442 void *idctl;
3462 3443
3463 3444 if ((mode & FREAD) == 0)
3464 3445 return (EPERM);
3465 3446
3466 3447 if (nioc->n_len < NVME_IDENTIFY_BUFSIZE)
3467 3448 return (EINVAL);
3468 3449
3469 3450 idctl = nvme_identify(nvme, nsid);
3470 3451 if (idctl == NULL)
3471 3452 return (EIO);
3472 3453
3473 3454 if (ddi_copyout(idctl, (void *)nioc->n_buf, NVME_IDENTIFY_BUFSIZE, mode)
3474 3455 != 0)
3475 3456 rv = EFAULT;
3476 3457
3477 3458 kmem_free(idctl, NVME_IDENTIFY_BUFSIZE);
3478 3459
3479 3460 return (rv);
3480 3461 }
3481 3462
3482 3463 static int
3483 3464 nvme_ioctl_capabilities(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3484 3465 int mode, cred_t *cred_p)
3485 3466 {
3486 3467 _NOTE(ARGUNUSED(nsid, cred_p));
3487 3468 int rv = 0;
3488 3469 nvme_reg_cap_t cap = { 0 };
3489 3470 nvme_capabilities_t nc;
3490 3471
3491 3472 if ((mode & FREAD) == 0)
3492 3473 return (EPERM);
3493 3474
3494 3475 if (nioc->n_len < sizeof (nc))
3495 3476 return (EINVAL);
3496 3477
3497 3478 cap.r = nvme_get64(nvme, NVME_REG_CAP);
3498 3479
3499 3480 /*
3500 3481 * The MPSMIN and MPSMAX fields in the CAP register use 0 to
3501 3482 * specify the base page size of 4k (1<<12), so add 12 here to
3502 3483 * get the real page size value.
3503 3484 */
3504 3485 nc.mpsmax = 1 << (12 + cap.b.cap_mpsmax);
3505 3486 nc.mpsmin = 1 << (12 + cap.b.cap_mpsmin);
3506 3487
3507 3488 if (ddi_copyout(&nc, (void *)nioc->n_buf, sizeof (nc), mode) != 0)
3508 3489 rv = EFAULT;
3509 3490
3510 3491 return (rv);
3511 3492 }
3512 3493
3513 3494 static int
3514 3495 nvme_ioctl_get_logpage(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3515 3496 int mode, cred_t *cred_p)
3516 3497 {
3517 3498 _NOTE(ARGUNUSED(cred_p));
3518 3499 void *log = NULL;
3519 3500 size_t bufsize = 0;
3520 3501 int rv = 0;
3521 3502
3522 3503 if ((mode & FREAD) == 0)
3523 3504 return (EPERM);
3524 3505
3525 3506 switch (nioc->n_arg) {
3526 3507 case NVME_LOGPAGE_ERROR:
3527 3508 if (nsid != 0)
3528 3509 return (EINVAL);
3529 3510 break;
3530 3511 case NVME_LOGPAGE_HEALTH:
3531 3512 if (nsid != 0 && nvme->n_idctl->id_lpa.lp_smart == 0)
3532 3513 return (EINVAL);
3533 3514
3534 3515 if (nsid == 0)
3535 3516 nsid = (uint32_t)-1;
3536 3517
3537 3518 break;
3538 3519 case NVME_LOGPAGE_FWSLOT:
3539 3520 if (nsid != 0)
3540 3521 return (EINVAL);
3541 3522 break;
3542 3523 default:
3543 3524 return (EINVAL);
3544 3525 }
3545 3526
3546 3527 if (nvme_get_logpage(nvme, &log, &bufsize, nioc->n_arg, nsid)
3547 3528 != DDI_SUCCESS)
3548 3529 return (EIO);
3549 3530
3550 3531 if (nioc->n_len < bufsize) {
3551 3532 kmem_free(log, bufsize);
3552 3533 return (EINVAL);
3553 3534 }
3554 3535
3555 3536 if (ddi_copyout(log, (void *)nioc->n_buf, bufsize, mode) != 0)
3556 3537 rv = EFAULT;
3557 3538
3558 3539 nioc->n_len = bufsize;
3559 3540 kmem_free(log, bufsize);
3560 3541
3561 3542 return (rv);
3562 3543 }
3563 3544
3564 3545 static int
3565 3546 nvme_ioctl_get_features(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc,
3566 3547 int mode, cred_t *cred_p)
3567 3548 {
3568 3549 _NOTE(ARGUNUSED(cred_p));
3569 3550 void *buf = NULL;
3570 3551 size_t bufsize = 0;
3571 3552 uint32_t res = 0;
3572 3553 uint8_t feature;
3573 3554 int rv = 0;
3574 3555
3575 3556 if ((mode & FREAD) == 0)
3576 3557 return (EPERM);
3577 3558
3578 3559 if ((nioc->n_arg >> 32) > 0xff)
3579 3560 return (EINVAL);
3580 3561
3581 3562 feature = (uint8_t)(nioc->n_arg >> 32);
3582 3563
3583 3564 switch (feature) {
3584 3565 case NVME_FEAT_ARBITRATION:
3585 3566 case NVME_FEAT_POWER_MGMT:
3586 3567 case NVME_FEAT_TEMPERATURE:
3587 3568 case NVME_FEAT_ERROR:
3588 3569 case NVME_FEAT_NQUEUES:
3589 3570 case NVME_FEAT_INTR_COAL:
3590 3571 case NVME_FEAT_WRITE_ATOM:
3591 3572 case NVME_FEAT_ASYNC_EVENT:
3592 3573 case NVME_FEAT_PROGRESS:
3593 3574 if (nsid != 0)
3594 3575 return (EINVAL);
3595 3576 break;
3596 3577
3597 3578 case NVME_FEAT_INTR_VECT:
3598 3579 if (nsid != 0)
3599 3580 return (EINVAL);
3600 3581
3601 3582 res = nioc->n_arg & 0xffffffffUL;
3602 3583 if (res >= nvme->n_intr_cnt)
3603 3584 return (EINVAL);
3604 3585 break;
3605 3586
3606 3587 case NVME_FEAT_LBA_RANGE:
3607 3588 if (nvme->n_lba_range_supported == B_FALSE)
3608 3589 return (EINVAL);
3609 3590
3610 3591 if (nsid == 0 ||
3611 3592 nsid > nvme->n_namespace_count)
3612 3593 return (EINVAL);
3613 3594
3614 3595 break;
3615 3596
3616 3597 case NVME_FEAT_WRITE_CACHE:
3617 3598 if (nsid != 0)
3618 3599 return (EINVAL);
3619 3600
3620 3601 if (!nvme->n_write_cache_present)
3621 3602 return (EINVAL);
3622 3603
3623 3604 break;
3624 3605
3625 3606 case NVME_FEAT_AUTO_PST:
3626 3607 if (nsid != 0)
3627 3608 return (EINVAL);
3628 3609
3629 3610 if (!nvme->n_auto_pst_supported)
3630 3611 return (EINVAL);
3631 3612
3632 3613 break;
3633 3614
3634 3615 default:
3635 3616 return (EINVAL);
3636 3617 }
3637 3618
3638 3619 if (nvme_get_features(nvme, nsid, feature, &res, &buf, &bufsize) ==
3639 3620 B_FALSE)
3640 3621 return (EIO);
3641 3622
3642 3623 if (nioc->n_len < bufsize) {
3643 3624 kmem_free(buf, bufsize);
3644 3625 return (EINVAL);
3645 3626 }
3646 3627
3647 3628 if (buf && ddi_copyout(buf, (void*)nioc->n_buf, bufsize, mode) != 0)
3648 3629 rv = EFAULT;
3649 3630
3650 3631 kmem_free(buf, bufsize);
3651 3632 nioc->n_arg = res;
3652 3633 nioc->n_len = bufsize;
3653 3634
3654 3635 return (rv);
3655 3636 }
3656 3637
3657 3638 static int
3658 3639 nvme_ioctl_intr_cnt(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3659 3640 cred_t *cred_p)
3660 3641 {
3661 3642 _NOTE(ARGUNUSED(nsid, mode, cred_p));
3662 3643
3663 3644 if ((mode & FREAD) == 0)
3664 3645 return (EPERM);
3665 3646
3666 3647 nioc->n_arg = nvme->n_intr_cnt;
3667 3648 return (0);
3668 3649 }
3669 3650
3670 3651 static int
3671 3652 nvme_ioctl_version(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3672 3653 cred_t *cred_p)
3673 3654 {
3674 3655 _NOTE(ARGUNUSED(nsid, cred_p));
3675 3656 int rv = 0;
3676 3657
3677 3658 if ((mode & FREAD) == 0)
3678 3659 return (EPERM);
3679 3660
3680 3661 if (nioc->n_len < sizeof (nvme->n_version))
3681 3662 return (ENOMEM);
3682 3663
3683 3664 if (ddi_copyout(&nvme->n_version, (void *)nioc->n_buf,
3684 3665 sizeof (nvme->n_version), mode) != 0)
3685 3666 rv = EFAULT;
3686 3667
3687 3668 return (rv);
3688 3669 }
3689 3670
3690 3671 static int
3691 3672 nvme_ioctl_format(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3692 3673 cred_t *cred_p)
3693 3674 {
3694 3675 _NOTE(ARGUNUSED(mode));
3695 3676 nvme_format_nvm_t frmt = { 0 };
3696 3677 int c_nsid = nsid != 0 ? nsid - 1 : 0;
3697 3678
3698 3679 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3699 3680 return (EPERM);
3700 3681
3701 3682 frmt.r = nioc->n_arg & 0xffffffff;
3702 3683
3703 3684 /*
3704 3685 * Check whether the FORMAT NVM command is supported.
3705 3686 */
3706 3687 if (nvme->n_idctl->id_oacs.oa_format == 0)
3707 3688 return (EINVAL);
3708 3689
3709 3690 /*
3710 3691 * Don't allow format or secure erase of individual namespace if that
3711 3692 * would cause a format or secure erase of all namespaces.
3712 3693 */
3713 3694 if (nsid != 0 && nvme->n_idctl->id_fna.fn_format != 0)
3714 3695 return (EINVAL);
3715 3696
3716 3697 if (nsid != 0 && frmt.b.fm_ses != NVME_FRMT_SES_NONE &&
3717 3698 nvme->n_idctl->id_fna.fn_sec_erase != 0)
3718 3699 return (EINVAL);
3719 3700
3720 3701 /*
3721 3702 * Don't allow formatting with Protection Information.
3722 3703 */
3723 3704 if (frmt.b.fm_pi != 0 || frmt.b.fm_pil != 0 || frmt.b.fm_ms != 0)
3724 3705 return (EINVAL);
3725 3706
3726 3707 /*
3727 3708 * Don't allow formatting using an illegal LBA format, or any LBA format
3728 3709 * that uses metadata.
3729 3710 */
3730 3711 if (frmt.b.fm_lbaf > nvme->n_ns[c_nsid].ns_idns->id_nlbaf ||
3731 3712 nvme->n_ns[c_nsid].ns_idns->id_lbaf[frmt.b.fm_lbaf].lbaf_ms != 0)
3732 3713 return (EINVAL);
3733 3714
3734 3715 /*
3735 3716 * Don't allow formatting using an illegal Secure Erase setting.
3736 3717 */
3737 3718 if (frmt.b.fm_ses > NVME_FRMT_MAX_SES ||
3738 3719 (frmt.b.fm_ses == NVME_FRMT_SES_CRYPTO &&
3739 3720 nvme->n_idctl->id_fna.fn_crypt_erase == 0))
3740 3721 return (EINVAL);
3741 3722
3742 3723 if (nsid == 0)
3743 3724 nsid = (uint32_t)-1;
3744 3725
3745 3726 return (nvme_format_nvm(nvme, nsid, frmt.b.fm_lbaf, B_FALSE, 0, B_FALSE,
3746 3727 frmt.b.fm_ses));
3747 3728 }
3748 3729
3749 3730 static int
3750 3731 nvme_ioctl_detach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3751 3732 cred_t *cred_p)
3752 3733 {
3753 3734 _NOTE(ARGUNUSED(nioc, mode));
3754 3735 int rv = 0;
3755 3736
3756 3737 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3757 3738 return (EPERM);
3758 3739
3759 3740 if (nsid == 0)
3760 3741 return (EINVAL);
3761 3742
3762 3743 rv = bd_detach_handle(nvme->n_ns[nsid - 1].ns_bd_hdl);
3763 3744 if (rv != DDI_SUCCESS)
3764 3745 rv = EBUSY;
3765 3746
3766 3747 return (rv);
3767 3748 }
3768 3749
3769 3750 static int
3770 3751 nvme_ioctl_attach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode,
3771 3752 cred_t *cred_p)
3772 3753 {
3773 3754 _NOTE(ARGUNUSED(nioc, mode));
3774 3755 nvme_identify_nsid_t *idns;
3775 3756 int rv = 0;
3776 3757
3777 3758 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0)
3778 3759 return (EPERM);
3779 3760
3780 3761 if (nsid == 0)
3781 3762 return (EINVAL);
3782 3763
3783 3764 /*
3784 3765 * Identify namespace again, free old identify data.
3785 3766 */
3786 3767 idns = nvme->n_ns[nsid - 1].ns_idns;
3787 3768 if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS)
3788 3769 return (EIO);
3789 3770
3790 3771 kmem_free(idns, sizeof (nvme_identify_nsid_t));
3791 3772
3792 3773 rv = bd_attach_handle(nvme->n_dip, nvme->n_ns[nsid - 1].ns_bd_hdl);
3793 3774 if (rv != DDI_SUCCESS)
3794 3775 rv = EBUSY;
3795 3776
3796 3777 return (rv);
3797 3778 }
3798 3779
3799 3780 static int
3800 3781 nvme_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred_p,
3801 3782 int *rval_p)
3802 3783 {
3803 3784 #ifndef __lock_lint
3804 3785 _NOTE(ARGUNUSED(rval_p));
3805 3786 #endif
3806 3787 minor_t minor = getminor(dev);
3807 3788 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor));
3808 3789 int nsid = NVME_MINOR_NSID(minor);
3809 3790 int rv = 0;
3810 3791 nvme_ioctl_t nioc;
3811 3792
3812 3793 int (*nvme_ioctl[])(nvme_t *, int, nvme_ioctl_t *, int, cred_t *) = {
3813 3794 NULL,
3814 3795 nvme_ioctl_identify,
3815 3796 nvme_ioctl_identify,
3816 3797 nvme_ioctl_capabilities,
3817 3798 nvme_ioctl_get_logpage,
3818 3799 nvme_ioctl_get_features,
3819 3800 nvme_ioctl_intr_cnt,
3820 3801 nvme_ioctl_version,
3821 3802 nvme_ioctl_format,
3822 3803 nvme_ioctl_detach,
3823 3804 nvme_ioctl_attach
3824 3805 };
3825 3806
3826 3807 if (nvme == NULL)
3827 3808 return (ENXIO);
3828 3809
3829 3810 if (nsid > nvme->n_namespace_count)
3830 3811 return (ENXIO);
3831 3812
3832 3813 if (IS_DEVCTL(cmd))
3833 3814 return (ndi_devctl_ioctl(nvme->n_dip, cmd, arg, mode, 0));
3834 3815
3835 3816 #ifdef _MULTI_DATAMODEL
3836 3817 switch (ddi_model_convert_from(mode & FMODELS)) {
3837 3818 case DDI_MODEL_ILP32: {
3838 3819 nvme_ioctl32_t nioc32;
3839 3820 if (ddi_copyin((void*)arg, &nioc32, sizeof (nvme_ioctl32_t),
3840 3821 mode) != 0)
3841 3822 return (EFAULT);
3842 3823 nioc.n_len = nioc32.n_len;
3843 3824 nioc.n_buf = nioc32.n_buf;
3844 3825 nioc.n_arg = nioc32.n_arg;
3845 3826 break;
3846 3827 }
3847 3828 case DDI_MODEL_NONE:
3848 3829 #endif
3849 3830 if (ddi_copyin((void*)arg, &nioc, sizeof (nvme_ioctl_t), mode)
3850 3831 != 0)
3851 3832 return (EFAULT);
3852 3833 #ifdef _MULTI_DATAMODEL
3853 3834 break;
3854 3835 }
3855 3836 #endif
3856 3837
3857 3838 if (cmd == NVME_IOC_IDENTIFY_CTRL) {
3858 3839 /*
3859 3840 * This makes NVME_IOC_IDENTIFY_CTRL work the same on devctl and
3860 3841 * attachment point nodes.
3861 3842 */
3862 3843 nsid = 0;
3863 3844 } else if (cmd == NVME_IOC_IDENTIFY_NSID && nsid == 0) {
3864 3845 /*
3865 3846 * This makes NVME_IOC_IDENTIFY_NSID work on a devctl node, it
3866 3847 * will always return identify data for namespace 1.
3867 3848 */
3868 3849 nsid = 1;
3869 3850 }
3870 3851
3871 3852 if (IS_NVME_IOC(cmd) && nvme_ioctl[NVME_IOC_CMD(cmd)] != NULL)
3872 3853 rv = nvme_ioctl[NVME_IOC_CMD(cmd)](nvme, nsid, &nioc, mode,
3873 3854 cred_p);
3874 3855 else
3875 3856 rv = EINVAL;
3876 3857
3877 3858 #ifdef _MULTI_DATAMODEL
3878 3859 switch (ddi_model_convert_from(mode & FMODELS)) {
3879 3860 case DDI_MODEL_ILP32: {
3880 3861 nvme_ioctl32_t nioc32;
3881 3862
3882 3863 nioc32.n_len = (size32_t)nioc.n_len;
3883 3864 nioc32.n_buf = (uintptr32_t)nioc.n_buf;
3884 3865 nioc32.n_arg = nioc.n_arg;
3885 3866
3886 3867 if (ddi_copyout(&nioc32, (void *)arg, sizeof (nvme_ioctl32_t),
3887 3868 mode) != 0)
3888 3869 return (EFAULT);
3889 3870 break;
3890 3871 }
3891 3872 case DDI_MODEL_NONE:
3892 3873 #endif
3893 3874 if (ddi_copyout(&nioc, (void *)arg, sizeof (nvme_ioctl_t), mode)
3894 3875 != 0)
3895 3876 return (EFAULT);
3896 3877 #ifdef _MULTI_DATAMODEL
3897 3878 break;
3898 3879 }
3899 3880 #endif
3900 3881
3901 3882 return (rv);
3902 3883 }
↓ open down ↓ |
580 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX